Altera, Xilinx hop diverging buses in SoC plans

Buses for system-on-chip devices have become a minor battleground now that the Virtual Socket Interface Alliance has decided that no single bus would become the VSIA standard. Instead, the group is espousing "wrappers" to tie components to any on-chip bus.

"Everyone has wanted a common on-chip bus to connect IP [intellectual property]," said Ed McGettigan, senior systems engineering manager at Xilinx. "Because [VSIA] has stalled, you see companies coming out with their own bus standards."

Hence IBM, ARM, Motorola Inc., PalmChip Corp. and others began offering their SoC buses to the silicon IP community, hoping to garner support in the form of IP cores created for the buses. The programmable-logic arena, where silicon IP is being combined with field-programmable gate arrays to creat e SoC devices, appears to be yet another vector for spreading each bus standard.

But lacking a standard, FPGA players eyeing SoC turf have to get a bus from somewhere, and making one of their own is out of the question. "If we foist a proprietary bus, that won't fly," said Brian Hoyer, Altera's senior director of system-level products.

Buses do exist that attempt to be processor-agnostic. PalmChip's CoreFrame is one, and in fact both Altera and Xilinx are partners in PalmChip's DirectConnect program for CoreFrame. But the introduction of hard processor cores gave the companies access to buses developed specifically for those CPUs.

That's not to say the bus developers are waging war for FPGA affections. The specific bus inside the chip doesn't make that much difference, said Max Baron, an analyst with Cahners In-Stat Group. Xilinx managers agreed; McGettigan noted that CoreConnect and Amba — both available in 128-bit versions — don't offer significant advantages over each other.

Nor will the FPGA vendors use their processor buses as selling points, Baron said. "The company that provides the core itself — Altera, for instance — will have to connect its masses of programmable logic to the core," he said. That responsibility won't fall to the user who's buying the chip, and Baron speculated that most customers won't particularly care which bus is inside it.

"As long as you don't put other embedded hard cores on chip I don't think the person who actually does the programming is affected," Baron said.

CoreConnect has no supporters besides Xilinx in the FPGA arena so far, but Amba already has been used by Lucent Technologies in FPGAs. Likewise, QuickLogic Corp. chief executive Thomas Hart has indicated that his company will use the Amba bus as well in its "embedded standard products." QuickLogic so far has allied with MIPS Technologies Inc. for those parts, and a second processor alliance is forthcoming in October, Hart said.

IBM has added high-performance features to CoreConnect not found in other buses, said Tom Collopy, PowerPC applications manager for IBM. Also, Collopy claimed CoreConnect is the only one of the bus options that is completely royalty-free.

Analyst Baron and others agreed that the programmable-logic arena alone won't decide which buses succeed. "On the ASIC side, things are a lot more fuzzy," he said — "especially with the introduction of soft cores, by almost everybody, that will go to different foundries."

Connecting with IBM

Xilinx and IBM in July announced a deal to create customized PowerPC hard cores to embed into the Virtex family of FPGAs. At the time, Bruce Weyer, Xilinx's senior director of marketing, said CoreConnect was a "huge part" of the agreement, as was "having a common process with an ASIC company."

"The real key is making sure the hard IP is tightly embedded in the fabric" of the FPGA, Weyer told EE Times last week. Using CoreConnect, Xil inx will be able to add hard cores anywhere in its FPGA, in any shape. Previously, cores were limited to particular columns within the array. "It's not only that we have a hard-core capability with PowerPC but the ability to handle much higher bandwidth," Weyer said.

In addition, Xilinx believes it will get extremely predictable performance from embedded cores. The Virtex architecture features a segmented routing structure that includes buffers at regular intervals to manage delays; this helps keep performance predictable and allows the placement of soft cores anywhere in the chip, Weyer said.

Virtex is constructed from an eight-metal-layer process technology. Hard cores will be built on the bottom four layers and the polysilicon underneath, leaving four more layers of metal for interconnect, Weyer said.

IBM began using CoreConnect five years ago as a way to facilitate design reuse. Beginning last year, the company began offering CoreConnect for licensing, hoping that adoption of the bus would le ad to more chip and IP sales for IBM. Xilinx is allowed to pass its CoreConnect license down to customers, but only for use within Xilinx parts.

At first blush, CoreConnect appears more suited for complex tasks and less toward low-power, low-end duties. Xilinx has not detailed the types of products it's targeting with its IP-cores program, but McGettigan noted that the company has tried Virtex with a wide variety of low-power processor cores. "If you want something really tiny and simple, it's there," he said.

Altera's CPU initiative, Excalibur, involves using the Apex FPGA to house one of three cores: the in-house soft core called Nios, or CPU hard cores from ARM or MIPS. Altera will disclose this week that Excalibur parts will use the Amba High-Performance Bus (AHB), one of the variants developed by ARM.

The choice stems partly from Altera's use of ARM cores — MIPS has no similar bus offering — but also is a result of LSI Logic Corp.'s decision to use Amba for both ARM and MIPS cores, Altera's Hoyer said.

Two AHBs will go inside an Excalibur chip. The user essentially connects the CPU to memory, isolating that link from the rest of the chip to ensure performance; the other serves all peripherals and external memory. Three AHB bridges allow the peripherals and PLD to communicate with the CPU.

For ARM, Amba's purpose is similar to how IBM sees CoreConnect — a way of facilitating processor sales for its parent company. That might work a little too well in the case of Excalibur, Baron said.

"The selection of Amba is very significant because it will tend to bias people" toward using Altera's ARM offerings rather than the MIPS-based devices, he said. "ARM has done a lot of homework not only in providing the bus but in building followers who provide [Amba-friendly] peripherals."

MIPS, on the other hand, simply allows its core to attach to multiple buses. "The very flexibility that MIPS has introduced by not adhering to a bus could cause some gravitation [among Altera users ] to ARM," Baron concluded.

This week, Altera also will disclose pricing and availability for the Excalibur parts, all built on Altera's Apex line. The XA1, XA4 and XA10 are increasingly larger chips based on the ARM922T core; the XM1, XM4 and XM10 are corresponding parts based on the MIPS32 4Kc.

First out the chute will be the XA10. Due to sample in December, it will be available in production volumes in the first quarter of 2001. Volume production of the XM10 should begin shortly afterward, and the remaining Excalibur parts are due to roll out in the first half of next year, said vice president of marketing Cliff Tong.

Volume pricing ranges from $35 to $700; in lots of 100 the price is $100 to $2,000.

Altera is still negotiating with Motorola for licensing the PowerPC. Tong declined to give specifics but said he expects Altera to offer PowerPC-based parts next year.

— Additional reporting by Rick Merritt.