Second StarCore DSP tuned for midrange apps

Second StarCore DSP tuned for midrange apps
By Patrick Mannion and Stephan Ohr, EE Times
September 18, 2000 (1:25 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000918S0049

DENVER — The joint StarCore operation of Motorola and Lucent Technologies is pitching its newest digital signal processor, the SC110, for use in low-end and midrange DSP applications such as 2.5- and third-generation telephones, Internet appliances, home networking client devices and voice-over-Internet access systems. This scaled-down version of the initial SC140 programmable DSP chip performs 300 million multiply-accumulate operations per second at 300 MHz, against 1,200 million for the SC140. At the same time, it boasts half the power consumption and a smaller die size.

"By scaling back, we get to meet the needs of applications that don't need the 140's performance, but also bring the idea of efficient compilability, allowing OEMs to develop more of their production software using the compiler," said Scott Beach, platform marketing manager at StarCore (Atlanta).

Platform leverage

By leveraging off the 140, the 110 can take full advantage of the highly optimized C compiler that is the architecture's trademark. This lets OEMs get up and running quickly, with minimal expectation of problems later in development, when they might be more costly to repair, the companies said. Meanwhile, until the SC110 becomes available from Motorola and Lucent early next year, developers can run and debug their code on the SC140 platform, then rapidly ramp to market when the SC110 does ship.

The companies are banking on communications to drive DSP market revenue for the next two to four years. Market research house Forward Concepts projects that the segment StarCore is targeting with the SC110 will make up some 32 percent of all DSP applications by 2002.

Introduced in April 1999, the SC140 core implementations from both Motorola (Austin, Texas) and Lucent (Allentown, Pa.) have emphasized its ability to add channels and conserve power in tightly packed, central-office switchers. Motorola, for exa mple, tweaked its MSC8101 for use as a network processor routing engine by adding an enhanced filter coprocessor and network protocol engine on top of on-chip SRAM and a PowerPC interface. Lucent's implementation, the StarPro family, is touted for an ability to process 64 full-rate asymmetric digital subscriber line channels.

From its inception, the StarCore design's very long instruction word (VLIW) architecture was intended to compete with Texas Instruments Inc.'s C6X family of DSPs. If the C6X's C-language compiler could operate at 100 percent efficiency, ensuring that every one of the chip's eight parallel parallel instruction execution units was utilized, the device could produce 1,600 Mips with a 200-MHz clock. If the compiler could not parallelize eight instructions, then the device produced something less than that, as the idling execution units continued to consume power.

Ability to scale

The Motorola-Lucent design was intended to reflect a tighter coupling between the capabi lities of a C compiler and the hardware it addressed, said Kevin Kloker, director of architecture for the StarCore project. It also has the ability to scale, using the modular architecture that StarCore executives touted from the beginning. Thus, the SC110 has scaled down the number of function units, the issue width and the bus width, he said.

"Scaling back the parallelism reduces costs and power consumption," Kloker said. "Instead of a six-issue machine, the StarCore becomes a three-issue machine; instead of four parallel MACs, the SC110 uses one."

But the SC110 matches the SC140 in the number of 16-bit address registers, dual 32-bit address-generation units and dual 32-bit data buses. The device can fetch four instruction words per clock over the 64-bit program data bus, and up to two prefix instructions per clock.

Power consumption is half that of the SC140: no more than 103 mW, running full bore at 300 MHz and 1.5 V (or 15 mW with a 0.9-V supply). "In addition," said Sanjay Bajekal, anoth er platform marketing manager, "the design uses the StarCore system's ability to automatically scale every transistor in the core for minimum power dissipation, while still meeting the speed requirements of all the critical paths."