Actel Offers One Million Gates for Free
Small, Downloadable Service Pack Adds Support for Actel Fusion PSC, ProASIC3 and ARM7-Enabled Devices
MOUNTAIN VIEW, Calif., February 21, 2006 — Continuing to enhance its tools suite with greater value, functionality and performance, Actel Corporation (NASDAQ: ACTL) today announced that its free Libero Gold Integrated Design Environment (IDE) now provides expanded device support for designs up to one million gates. Users need only download and install a small service pack, the Libero 7.0 IDE Service Pack 1 (SP1), to their existing Libero 7.0 IDE software to immediately start developing one million-gate designs using Actel's field-programmable gate arrays (FPGAs). This free, expanded device support covers all Actel single-chip device families, including the company's low-cost ProASIC3 and ARM7-enabled ProASIC3 FPGA families, and the world's first mixed-signal FPGA, the Actel Fusion Programmable System Chip (PSC).
For the Actel Fusion PSC, Libero 7.0 SP1 also provides enhanced SmartGen Fusion IP peripheral generation flows that streamline the configuration of Analog System Builder Components. In addition, the service pack includes enhanced algorithms that dramatically improve the place-and-route efficiency and quality of results (QoR) for Actel's high-performance, antifuse-based Axcelerator FPGAs. Five effort levels for Axcelerator timing-driven layout have been re-tuned to function in "quick mode," providing up to twice the runtime performance with improved QoR.
"This release reflects Actel's commitment to deliver easy-to-use and cost-efficient tools for the development of high-performance designs," said Jake Chuang, senior director of tools marketing at Actel. "In addition to enabling our customers to design up to one million gates for free, the service pack adds support for the Actel Fusion PSC and ARM7-enabled ProASIC3 devices, allowing our customers to immediately begin their mixed-signal and embedded system designs."
The Libero IDE Gold software contains all the tools of Libero IDE Platinum, except PALACE AE Physical Synthesis, and WaveFormer Lite Reactive Test Bench and VCD import. Device support for Actel's Libero Gold now includes:
- Fusion: AFS250, 600
- ProASIC3E: A3PE600
- ProASIC3: A3P060, 125, 250, 400, 600, 1000
- ARM7 ProASIC3E: M7A3PE600
- ARM7 ProASIC3: M7A3P250, 1000
- ProASICPLUS: APA075, 150, 300, 450, 600, 1000
- Axcelerator: AX125, 250, 500, 1000
- Radiation-tolerant Axcelerator: RTAX250, 1000S
Availability
Libero IDE 7.0 SP1 is available immediately as a free software download from Actel's Web site, www.actel.com. Users must already have Libero IDE 7.0 installed or they can get a free copy of Libero IDE 7.0, along with a free Libero Gold software license, from Actel's Web site.
About Actel
Actel Corporation is the leader in single-chip FPGA solutions. The Company is traded on the NASDAQ National Market under the symbol ACTL and is headquartered at 2061 Stierlin Court, Mountain View, Calif., 94043-4655. For more information about Actel, visit http://www.actel.com. Telephone: 888-99-ACTEL (992-2835).
|
Microsemi Hot IP
Related News
- Actel Offers Free, Optimized ARM Cortex-M1 Processor for Industry's Lowest Power FPGA Family
- Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation.
- ARM Offers Free Access to Cortex-M0 Processor IP to Streamline Embedded SoC Design
- Aldec Announces HES-7, the Largest Off-The-Shelf Xilinx Virtex-7 FPGA Prototyping System at up to 288 Million ASIC Gates Capacity
- Reflex CES Enters Mainstream FPGA-Prototyping Market; Offers 25-Million Gates or More ASIC Prototyping Platform With Partitioning Software
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X
E-mail This Article | Printer-Friendly Page |