Tools blend analog, digital design flows

Tools blend analog, digital design flows
By Stephan Ohr, EE Times
September 11, 2000 (1:38 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000911S0034

SCOTTS VALLEY, Calif. — Three years after starting to develop a top-down design flow for analog ICs — one that would coalesce into something called "synthesis" — Antrim Design Systems is announcing a tool suite said to fill many of the gaps between high-level architectural design and analog intellectual-property creation. Called Antrim-ACV (for analysis, characterization and verification), the tool suite is intended to fit analog design into the same flows used by digital designers.

Analog and mixed-signal tools for the desktop are in demand by makers of consumer and communications ICs, said Nelson Seiden, Antrim's director of marketing. The Antrim-ACV tool set, which integrates with the Cadence Analog Composer design capture environment, allows high-level architectural topology capture (a "spec sheet") but uses it to generate detailed analysis and verification plans and even test suites.

The Antrim tool set addresses the proble ms of design productivity (both for experienced and novice analog designers), particularly design reuse. Analog designers are often poorly supported and cannot cope with specification changes late in the design cycle, Seiden said. Antrim-AVC effectively automates the simulation and verification planning cycle, making it easier for designers to replicate previously run simulations and tests with new specifications for a device-under-test.

The designs and their test plans are captured in the equivalent of an Excel spreadsheet, Seiden said. The tool looks at simulation results and comes up with a validated spec. That spec, in turn, can create a tradable, verifiable analog IP block. Indeed, Antrim-ACV's creators call it an IP delivery vehicle.

"We're starting to automate the analog side of things," said Seiden. Matsushita (Osaka, Japan) used the tool set to build single-chip DVD players and components for cell phones. Other much-sought blocks, especially for communications applications, include voltage- controlled oscillators, interpolating A/D converters and phase-locked loops (PLLs).

While the analysis, characterization and verification vehicle will generate test plans and add them to a cell model (or IP), its execution will obviously depend on fast simulation. The Antrim tools use "burst" simulation, said to improve run-time by allowing multiple simulators to run in parallel. "In operation, the simulation run is partitioned into lots of little simulations," sometimes thousands, Seiden said. The simulators are in effect "checked in" and "checked out" as needed for each task. "We license them instantaneously for each job," he said.

The Verilog-A and HSpice simulation capability built into the Antrim flow allows for optimization, reliability analysis with Monte Carlo simulation and even what Seiden calls "corners analysis," with fast signals stimulating slow devices and slow signals stimulating fast devices (fast/fast and slow/slow are possible as well). "You can really take advantage of a computer farm," Seiden said.

Optimization for the spec generator lets designers find the lowest-power-consuming cells, the smallest silicon area or a suitable trade-off between them. "This allows companies to get in and develop their secret sauce," Seiden said.

He said the tool set is particularly useful for process migration and retargeting — for example, for moving a 0.25-micron CMOS design from Taiwan Semiconductor Manufacturing Co. to United Microelectronics Corp.'s 0.25-micron process. Seiden said the ACV output is effectively a new electronic spec that Antrim believes is a launchpad to synthesis.

Antrim-ACV runs on Unix and costs $50,000 to integrate into the Cadence Composer design environment.