Silicon Interfaces announces the release of its new Verification Intellectual Property USB OTG Vera RVM VIP

CAMPBELL, Calif. -- April 19, 2006 - Silicon Interfaces, a high-end design services and leading provider for IP’s in Europe, North America and Asia-Pacific, under their IP Development Program - Silicon Cores: Core to the Intelligent Systems™, today announced the availability of USB OTG Vera RVM VIP, intellectual property. The SI70OTGRVM10, USB OTG Vera RVM VIP increases the portfolio of Silicon Interfaces Verification IP’s.

Silicon Interfaces’ USB OTG Vera RVM VIP is fully documented, off the shelf component for the verification of the USB OTG Dual-Role Device.

This VIP is developed using the Synopsys’ OpenVera Reference Verification Methodology that is used in dynamic simulation of USB OTG based design.

The RVM methodology is based on the following cornerstones

Constrained random stimulus generation raises the abstraction level in test bench code.
DFV improves the observability of design errors by providing means for an abstract specification of the Device behavior using assertions.
Reusable test benches and reusable assertion-based checkers reduce the effort needed to verify complex Devices and interface protocols.

The objective of RVM methodology is to create a test environment with the following characteristics or features

Use functional coverage metrics to direct the verification effort and measure progress.
Maximum use of random stimulus.
Creation and use of reusable verification components.
Portability across various levels of abstraction of the DUT.
Portability from block-level to system-level.

The VIP provides a fast, accurate way to simplify and speed-up the device verification task in a complex design process, verification can take up to 70% of the development time.

USB OTG Vera RVM VIP speeds up the verification process providing a compelling cost and time to market. Object Oriented Programming approach plays one of the key roles to achieve these goals. Writing a reusable code makes it easy for the Verification Engineer to apply the same tasks in various modules from project-to-project and code is maintainable.

SI70OTGRVM10, USB OTG Vera RVM VIP Specifications

The VIP can work with 8-bit or 16-bit standard USB OTG Dual-Role devices.
Error Injection Mechanism, which can be turned ON or OFF for a given simulation run.
Incorporated around 50 scenarios for different Error types Provides a choice for RESETTING to either High-Speed or Full-Speed mode upon startup.
Supports RESET/SUSPEND/RESUME. On-the-fly Reset switch over from High-Speed to Full-Speed or vice-versa supported.

SI70OTGRVM10, USB OTG Vera RVM VIP Features

Synopsys RVM compliant
Absence of inter-module dependencies makes the VIP highly reusable
Programmable and Randomized Transfer Types, namely INTERRUPT, ISOCHRONOUS, BULK and CONTROL
Hierarchical Seed Randomization.
Fully Constraints Driven Randomization of various fields of the Packets on both the interface ends of the IP
Initial DUT Health Checkup Mechanism
On-the-fly change in the role of the device from OTG A-Device to OTG B-Device or viceversa with Host Negotiation Protocol (HNP)
Support for Session Request Protocol (SRP) under Host functionality
Choice for inhibiting SUSPEND and / or RESET operation through use of simple macros
The product is bundled with a very fancy, intelligent and versatile Scoreboard that provides:

A bird’s eye view of the USB Transactions
Total number of Transactions and transfers with a split on successful / failure in various speeds and modes
Count of Token, Data and Handshake Packets sent / received
Status of transactions on supported / unsupported Device Addresses and Endpoint Adresses
Statistics on RESET / SUSPEND / RESUME activities
Error Injection statistics
Overall count of good / bad Packets

For a complete listing of features and pricing of, SI70OTGRVM10, USB OTG Vera RVM VIP please contact Silicon Cores

Availability

The SI70OTGRVM10, USB OTG Vera RVM VIP is available now. USB OTG Vera RVM VIP can work in a standalone mode i.e. it can be plugged with any OTG Dual-Role Device with standard pin-outs without disturbing the structure of the front-end bus (UTMI+).

About Silicon Interfaces

Silicon Interfaces has experience in verification solutions and developing IP for Fabric Channel Interconnect, Telecom and Networking domains, including Bluetooth Baseband, 802.11 a/b/g MAC & Baseband, Gigabit Ethernet MAC, Sonet STS 1/3 Framer, 1394, USB2 Function Controller, USB On-the-Go, Infiniband, Rapid IO, 8530, 8051, 7990 and UART. Currently, our Roadmap IPs are PCI-Express, 10 Giga and SONET STS Framer –12. The IPs has had considerable maturity based on certification, targets to various FPGA devices and ASIC libraries, silicon area optimization, silicon prototyping and testing. Also available is OVA VIP’s and an extensive driver development program in order to offer a packaged solution to the customer.