Startup SpeedGate promised better FPGA partitioning

The company's mission is to provide a "front end for what is commonly known as roll-your-own emulation," said Martin. Its initial product is aimed at customers building their own emulation systems using FPGAs and custom boards. But SpeedGate is also seeking funding for some future plans in the simulation acceleration area, he said.

Martin said there are two types of emulation in the market today — "black box" emulation, as provided by companies like Cadence's Quickturn division; and "open-system" or roll-your-own emulation. "There's a real hole in the market," he said. "Black-box emulation is too expensi ve and becomes obsolete very quickly. Roll-your-own has a lot of merit; it's low-cost, and you can jump on new FPGAs as they come out. But the problem is stuffing the FPGAs."

I/O distribution addressed

That problem is addressed by FPGA Stuffer, an interactive partitioning tool. Key to the product is its claimed ability to solve the I/O distribution problem among multiple FPGAs. SpeedGate accomplishes this by working at an "intermediate" level of granularity that makes RTL partitioning more practical, the company claims.

As a result, said Martin, FPGA Stuffer allows faster emulation, preserves signal visibility and handles very large databases — all features that he said are missing in most comparable products today. Further, he noted, it can work with any script-based third-party synthesis tool, and it helps speed up synthesis on large designs.

More than just a partitioner, Martin said, FPGA Stuffer is an "environment" from which FPGA synthesis and placement and routing can be launched. He said the product has partitioned databases as large as 12 million gates. Today, the tool works only with Xilinx Inc.'s Virtex FPGAs.

"There's a special format that goes into their place and route, and we don't want to take on another FPGA at this point," Martin said. But there's nothing to prevent SpeedGate from supporting other FPGA vendors in the future, he said.

The biggest problem in multiple-FPGA partitioning, Martin said, is I/O distribution. "Most designs today are I/O bound," he said. "You end up hitting the I/O limit of the FPGAs more than the total logic capacity size."

Previous approaches, he said, have tried to partition at the module or gate level. The module level is the smallest entity at the register-transfer level, but it provides a limited number of solutions, making it difficult to find an I/O solution. The gate level provides too much granularity, and the database becomes unmanageable, Martin said.

As a result, he claimed, other tools resort to a time-domain multiplexing scheme that allows single pins to handle multiple signals. But this results in a speed penalty, and makes in-circuit emulation difficult, Martin said.

Faced with approaches that are too granular and not granular enough, SpeedGate believes it has found the approach that is "just right." FPGA Stuffer partitions at the process level. That's one step down from the module level, since modules are collections of processes and instantiations of other modules. In Verilog, an "always" block or a continuous-assignment statement typically denotes a process.

"This allows us to break down a module into smaller pieces that are functionally intact, move them around and distribute them," said Shalish. "It allows you to do RTL partitioning, and provides more options for solving the I/O problem."

A key advantage of this approach, said Martin, is retention of RTL signal names. These are typically lost because synthesis changes the names. "If you don't know what the names are during debugging, you have a major problem," he said. "Most people go through a correlation process, which is a major bottleneck."

FPGA Stuffer, it should be noted, offers interactive partitioning — it's not an automatic product. It helps with analysis, but the user still partitions the netlist, either graphically or using text scripts. But FPGA Stuffer does offer an interface to H-metis, a public-domain automatic partitioning program.

Synthesis first

Input to FPGA Stuffer consists of RTL Verilog code, with VHDL support to follow later. The product then builds a database, decomposes the design and kicks of FPGA synthesis. It may seem odd that RTL partitioning is done after synthesis, but FPGA Stuffer needs the results of synthesis, including logic, clocking and I/O information, before doing the partitioning among multiple FPGAs.

FPGA Stuffer has what Shalish called "impact-analysis and helper tools" to help guide the interactive partitioning. For example, the program can flag the user when an FPGA is o ver 80 percent full, or if it's over a specified I/O count. It can provide a list of the best possible moves to reduce the I/O. The tool also gives a "connectivity matrix" that lets users view connectivity between processes and modules in a hierarchy.

The output of FPGA Stuffer consists of a partitioned RTL Verilog netlist and an EDIF file for each FPGA. The EDIF file can go into Xilinx placement and routing tools. FPGA Stuffer also spits out an EDIF file for board-level interconnect between the FPGAs.

The initial release supports Synopsys FPGA Compiler II and FPGA Express, and Synplicity's Synplify synthesis tools. Users can add other synthesis tools that have a scripted interface. The product runs on Sun Solaris platforms.

SpeedGate intends to sell partially through OEM deals, and has one with emulation startup AppNet Inc., which provides the Proteus prototyping platform.