With XScale, Intel weighs in on mobile Internet

As with the StrongARM, Mi ps per watt is a major selling point of the new architecture. At 0.75-volt and 50-MHz operation, "you can run the core, without the cache, for about a week on a single AA battery," said Jay Heeb, the engineering director of the XScale design team, speaking at the Intel Developer Forum here this past week.

Ron Smith, corporate vice president and general manager of Intel's wireless-communications and computing group, demonstrated first silicon at the forum, pushing the test chip as high as 1 GHz and 1,250 Mips. "With XScale's ability to scale down to 125 Mips at 10 milliwatts, manufacturers can now start replacing rechargeable batteries with a single, throwaway AA," Smith said.

"What's really impressive is that the same architecture can be implemented in a wide range of applications," said Linley Gwennap, principal analyst with The Linley Group (Mountain View, Calif.). He pointed to the Au series of processors from Alchemy Semiconductor (Austin) as probably the closest thing in the industry to the XS cale.

"However, there is an advantage to being Intel," Gwennap said. "Companies will be more willing to buy their silicon from Intel than from some little startup no one has heard of."

Smith said that by the fourth quarter Intel will deliver enhanced software, the Intel Integrated Performance Primitives (IIP), to ease application development on the XScale, IA-32 and IA-64 architectures. IIP would support parallel development of hardware and applications.

Smith also outlined a communications system design that he called "a paradigm shift." It would decouple the computing and communications stacks to enable a more parallel development process.

Smith emphasized the XScale microarchitecture's scalabil-ity. With support from future operating systems, its frequency can be adapted on the fly, with the supply voltage kept as low as 0.75 V for the simplest tasks and raised much higher as the situation demands. In sleep mode, the core will consume as little as a 10,000th of a watt, or 0.05 milliwatt. For standby mode, Heeb said, Intel engineers devised a way to save the processor state, turn off the phase-locked loop circuit and turn the processor core and cache back on in about 20 microseconds.

For dense, tethered systems where moderate power consumption can obviate the need for a fan, the architecture could use a 1.65-V supply and rev up to 1,000 Dhrystone Mips at 800 MHz, with the active power consumption at a respectable 1 W.

The microarchitecture is based on an ARM 5TE-compliant core, surrounded by a slew of enabling logic. The "T" in 5TE refers to the Thumb 16-bit instruction set, which can be selected via the current program status register.

The overall intent of the microarchitecture is to let designers combine XScale with peripherals to provide application-specific standard products for target markets. Typically, the core can be integrated with peripherals such as an LCD controller, multimedia controllers and external memory interface. Alternatively, the microarchitecture could be surrounded by high-bandwidth PCI interfaces, memory controllers and networking microengines to provide a highly integrated, low-power I/O or network processor.

It currently uses an 0.18-micron process, but Intel plans to move to 0.13 micron, probably in 2002.

The microarchitecture is one of a number of mobile Internet building blocks Intel has created or acquired. Already the leading flash-memory provider for mobile devices, the company acquired leading-edge baseband-processing expertise through its purchase of DSP Communications last year, and is in cahoots with Analog Devices to corner the mobile DSP market. The much-anticipated results of this partnership are expected "later this year," said Smith.

To achieve the performance and power capabilities touted in the XScale, Intel incorporated three core competencies: a dynamic voltage-management scheme, superpipelined technology and media-processing technology. In addition, the core is designed with power-saving techniques that power up a functio nal block only when it's needed. This saves power by matching the core clock frequency to the current workload. The superpipeline comprises the integer (seven stages), MAC (six to nine stages) and memory (eight stages) pipes.

Voltage, frequency shifts

The core can change frequency on a cycle-by-cycle basis, but switching the voltage would take several milliseconds.

Intel requires OS support for dynamic voltage management, and that will take time, said analyst Gwennap. He pointed to similarities with what Transmeta Corp. has done in terms of varying the voltage and frequency of its Crusoe processor, and to work at Intel and Advanced Micro Devices to vary the voltage in their mobile processors.

"It takes quite a bit of engineering to be able to change the voltage on the fly, and to ensure that at no point does the chip stop working. That takes extra simulation work and, on the manufacturing side, extra testing," Gwennap said. "Certainly not everybody will do both with it [varying th e frequency and the voltage]. A lot of people will pick a performance point and stick with a fixed supply voltage."

He added that while a PDA company might want to change the frequency on the fly, that will require support from the operating system to tell the chip to supply more power when, say, a videoconferencing application kicks in.

The third leg of the XScale design — the media-processing technology — is a special set of multimedia instructions, similar to the SIMD instructions going into the IA architecture. The instructions allow the MAC coprocessor to perform two simultaneous 16-bit single-instruction, multiple-data (SIMD) multiplies with 40-bit accumulation for efficient media processing. "The aim," said Smith, "is to facilitate the development of multimedia applications around XScale."

Over the coming months, Intel will announce support for other applications. For the infrastructure, these will include line-access cards and digital subscriber line access multiplexers, as w ell as routing and storage support for networking. For mobile clients, the company is targeting wireless LANs and, of course, PDAs.

Heeb created a somewhat futuristic scenario in which a wireless-system user might be penning in a memo, using relatively little power as the core operates at a low supply voltage. Then, as his wife calls, the power scales up past 1 V. As his wife beams a streaming video of their child taking his first steps, the XScale moves up to full performance.

"We want to provide performance on demand, but at no more power than necessary," Heeb said.

Intel also has its eye on the mobile phone market, but it has its work cut out for it in that arena, said Ken Delaney, an analyst with Dataquest-Gartner Group, based in Stamford, Conn. "While it may well be good technology," he said, "in the end it could be more a political rather than technological hurdle they [Intel] face. European companies tend to feel that U.S. companies want to steamroll them, hence they tend to favor homegro wn technologies, such as ARM, out of the U.K. Considering the share Ericsson and Nokia have of the mobile phone market, this could play a major role in Intel's ability to penetrate."

On the software side, Smith said the Intel Integrated Performance Primitives will support the rapid development of applications. These OS-independent and pre-optimized lines of code for audio, video and graphics are designed to speed the development of multimedia apps for Intel's complete line of processors, from StrongARM and XScale to the IA-32 and IA-64 CPUs.

Smith said that the time it takes to develop a new phone is compounded not only by software development, but by governmental and regulatory approvals. The delays can seriously jeopardize a design's success at a time when market windows are measured in Internet time.

To overcome this, Smith announced Intel's intention to decouple the computing and communications stacks to enable a more parallel development process. "The computing element is developing much fa ster than the communications end, thanks to demands resulting from intensive applications processing in the packet data era," he said.

As wireless moves to packet data delivery, Smith said additional computing power will help users keep track of packet billing. "You want to at least be as smart as your service provider so you can dispute the bill," he said.

The first chips based on Intel's XScale microarchitecture should ship by the end of the year. Throughout 2001, a range of products, and optimized silicon for certain customers, will become available, the company said.

— Additional reporting by David Lammers