CEVA Expands CEVA-X DSP Family with New Core and System Platform
CEVA-X1622 is a high-performance, low-power, fully synthesizable DSP with enhanced memory architecture, including configurable memory size (64KB or 128KB) and configurable memory bank organization in 2 or 4 blocks. The flexible memory architecture allows the customer to make an optimal cost/performance selection in line with market needs. In addition, the CEVA-X1622 core offers a reduced gate count compared to other CEVA-X family members. Using an area-optimized implementation and On-chip Emulation Module (OCEM) enhancements, the core achieves a significant area reduction compared to the CEVA-X1620, making it ideal for advanced baseband and other mobile applications.
The CEVA-XS1102 is a complete DSP system platform built around the CEVA-X1622 DSP core, and includes additional peripherals and system interfaces for efficient system design.
CEVA-XS1102 benefits to customers include reduced development costs and time to market, coupled with the user flexibility and reduced area offered by the CEVA-X1622 DSP core.
CEVA-X1622 offers backward code compatibility to the CEVA-X1620 DSP, enabling licensees of the CEVA-X1622 DSP to leverage the broad range of software and components already available for the CEVA-X architecture.
“These newest additions to the highly successful family of CEVA-X DSP cores and platforms deliver important enhancements that will enable critical differentiation in communications and consumer applications,” said Gideon Wertheizer, CEO of CEVA, Inc. “The CEVA-X1622 strengthens our breadth of offerings in leading-edge DSP core technology with a solution that lowers cost and reduces die size.”
The CEVA-X1622 DSP core features a 16-bit fixed-point dual-MAC Very Long Instruction Word (VLIW) architecture combined with a Single Instruction Multiple Data (SIMD) multimedia operations, up to eight instructions executed in parallel, variable instruction widths (16- or 32-bit) and 4GB of byte-addressable memory space. Numerous multimedia instructions and mechanisms built into the CEVA-X architecture enable the processor to dramatically accelerate advanced video compression standards on a truly software programmable platform. Furthermore, the innovative, reusable architecture of the CEVA-X provides customers with comprehensive deployment flexibility within a unified architecture framework. CEVA-X enables efficient programming in C/C++ high-level languages that significantly reduces development costs and time to market.
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is the leading licensor of digital signal processor (DSP) cores, multimedia, GPS and storage platforms to the semiconductor industry. CEVA licenses a family of programmable DSP cores, associated SoC system platforms and a portfolio of application platforms including multimedia, audio, Voice over Packet (VoP), GPS location, Bluetooth, Serial Attached SCSI and Serial ATA (SATA). In 2005, CEVA's IP was shipped in over 130 million devices. For more information visit www.ceva-dsp.com
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