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TSMC 65-Nanometer Process Moves to Volume Production
Foundry’s First Production-ready Node Drives High Value, Low Risk and Easy Adoption
Hsinchu, Taiwan, R.O.C. - May 17, 2006 - Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65-nanometer (nm) low power process technology. The announcement officially opens the doors for TSMC to deliver the production-ready 65nm process.
With several products already ramped and delivering production volumes, the new process provides higher levels of integration and performance improvement with groundbreaking power management technology for the lowest possible power usage. The new 65nm process is supported by TSMC’s Design Support Ecosystem, featuring DFM-compliant 65nm products and services; by TSMC’s Reference Flow 6.0 design methodology; and by a variety of process-proven TSMC and third-party libraries and IP.
“TSMC again leads the industry in pushing Moore’s law to the 65 nanometer generation,” said Dr. Rick Tsai, President and Chief Executive Officer, TSMC. “At 65nm geometries, we can produce highly integrated, very small and low power devices for every conceivable market. Producing on our advanced 300mm wafers, we can ramp customer’s design to high volume quickly. It provides unprecedented opportunities for customers to further advance the leadership positions in their marketplaces.”
TSMC’s 65nm NexsysSM technology is the company’s third-generation semiconductor process employing both copper interconnects and low-k dielectrics. It is a 9-layer metal process with core voltages of 1.0 or 1.2 volts, and I/O voltages of 1.8, 2.5 or 3.3 volts. The new technology offering supports a standard cell gate density twice that of TSMC’s 90nm NexsysSM process. It also features very competitive 6T SRAM and 1T embedded DRAM memory cell sizes. In addition, this technology offering includes mixed signal and radio frequency functionality to support analog and wireless design, embedded high density memory to support integration of logic and memory, and electrical fuse to support customer encryption needs.
About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
Hsinchu, Taiwan, R.O.C. - May 17, 2006 - Taiwan Semiconductor Manufacturing Company today told a packed audience at its 2006 Technology Symposium that the company has fully qualified its 65-nanometer (nm) low power process technology. The announcement officially opens the doors for TSMC to deliver the production-ready 65nm process.
With several products already ramped and delivering production volumes, the new process provides higher levels of integration and performance improvement with groundbreaking power management technology for the lowest possible power usage. The new 65nm process is supported by TSMC’s Design Support Ecosystem, featuring DFM-compliant 65nm products and services; by TSMC’s Reference Flow 6.0 design methodology; and by a variety of process-proven TSMC and third-party libraries and IP.
“TSMC again leads the industry in pushing Moore’s law to the 65 nanometer generation,” said Dr. Rick Tsai, President and Chief Executive Officer, TSMC. “At 65nm geometries, we can produce highly integrated, very small and low power devices for every conceivable market. Producing on our advanced 300mm wafers, we can ramp customer’s design to high volume quickly. It provides unprecedented opportunities for customers to further advance the leadership positions in their marketplaces.”
TSMC’s 65nm NexsysSM technology is the company’s third-generation semiconductor process employing both copper interconnects and low-k dielectrics. It is a 9-layer metal process with core voltages of 1.0 or 1.2 volts, and I/O voltages of 1.8, 2.5 or 3.3 volts. The new technology offering supports a standard cell gate density twice that of TSMC’s 90nm NexsysSM process. It also features very competitive 6T SRAM and 1T embedded DRAM memory cell sizes. In addition, this technology offering includes mixed signal and radio frequency functionality to support analog and wireless design, embedded high density memory to support integration of logic and memory, and electrical fuse to support customer encryption needs.
About TSMC
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.
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