400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Pre-Fab Chip Design Takes Root
Electronic News
The chip-building industry is turning to a new pre-fab approach, as companies look to simplify the design and creation of new chips at advanced process nodes.
Faced with a shrinking market for new system-on-a-chip designs if costs and time-to-market concerns aren’t solved, a number of established players have begun rolling out new pre-packaged solutions. IBM, Samsung and Chartered Semiconductor, for example, have banded together to create design for manufacturing kits.
In the EDA world, Cadence Design Systems has created its own design kits that work with those kits. And Synopsys has created an expanded design for manufacturing flow that roughly accomplishes the same thing. And in the IP world, companies such as Rambus and Tensilica have offered up packages of that are backed by a portfolio of proven relevant patents. In Rambus’ case, those patents are for intellectual property, plus options for additional services. In Tensilica’s case, it is patents coupled with off-the-shelf synthesizable cores.
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