400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
IP reuse on the rise, says Synopsys CEO
(05/30/2006 11:50 AM EDT)
BANGALORE, India — Chip design companies, in particular startup companies in China and Israel, are increasing their adoption of reusable IP, according to Aart de Geus, chairman and CEO, Synopsys.
During a visit to Synopsys' India design center here, de Geus said, "My view is that IP re-use is an absolutely key ingredient for modern-day design, especially when design challenges are rising with the movement towards smaller geometries."
In its ongoing study of nearly 200 active 65-nm designs, Synopsys (Mountain View, Calif.) has found that the most difficult aspects is the struggle with power consumption. "One of the techniques that we have fully implemented in our tools is the ability to run different portions of a chip at different voltages," de Geus said.
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