English
Panelists explore system-to-silicon link
Richard Goering, EE Times
(05/31/2006 10:53 AM EDT)
PRIEN, Germany — How can designers produce manufacturable silicon from system-level specifications? Panelists at the Medea+DAC (Design Automation Conference) here had some suggestions Tuesday (May 30), including formal specifications, abstracted hardware-software interfaces and the use of regularity in silicon fabrics.
Panel moderator Joseph Borel, retired vice president of STMicroelectronics, noted that total development costs for 65-nm chips are nearing $40 million, making it more important than ever to get designs right the first time. He called for "applications design platforms" in which formal specs can be reduced to RTL design, and physical layout is aware of design-for-manufacturability (DFM) issues.
Eric Bantegnie, president of Esterel Technologies, presented formal modeling languages as an enabler for electronic system level (ESL) design. "You can automate the ESL to RTL link if you build ESL on solid formal foundations," he said.
(05/31/2006 10:53 AM EDT)
PRIEN, Germany — How can designers produce manufacturable silicon from system-level specifications? Panelists at the Medea+DAC (Design Automation Conference) here had some suggestions Tuesday (May 30), including formal specifications, abstracted hardware-software interfaces and the use of regularity in silicon fabrics.
Panel moderator Joseph Borel, retired vice president of STMicroelectronics, noted that total development costs for 65-nm chips are nearing $40 million, making it more important than ever to get designs right the first time. He called for "applications design platforms" in which formal specs can be reduced to RTL design, and physical layout is aware of design-for-manufacturability (DFM) issues.
Eric Bantegnie, president of Esterel Technologies, presented formal modeling languages as an enabler for electronic system level (ESL) design. "You can automate the ESL to RTL link if you build ESL on solid formal foundations," he said.
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