Altera POS-PHY cores suit PMC-Sierra products
Altera POS-PHY cores suit PMC-Sierra products
By Michael Santarini, EE Times
August 14, 2000 (11:01 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000814S0008
Altera Corp. (San Jose, Calif.) has announced a family of cores that are compatible with PMC-Sierra's line of POS-PHY Level 3 products.
According to the company, the first core in the family is currently shipping to selected top-tier network infrastructure customers using PMC-Sierra products for the new generation of super routers and Layer 3 switches that are required for next-generation, multiservice voice and data networks.
Altera also announced that it will continue to work closely with PMC-Sierra to ensure that future core offerings have device compatibility with POS-PHY Level 3 and beyond. The company said it is currently participating in the definition of the POS-PHY Level 4 standard.
Altera's POS-PHY Level 3 cores are designed for use in link-layer or physical-layer devices that transfer data to and from POS devices using the standard POS-PHY interface.
The MegaCore functions comprise separately configurable mo dules that may be combined via Altera's MegaWizard Plug-In tool to generate a parameterized module that allows POS-PHY-compliant interfaces to be included in custom designs, said Altera.
The MegaCore function supports POS-PHY Level 3 operating at greater than OC-48 line speeds (2.5 Gbits/second), enabling efficient translation between the different formats, including mapping between different bus speeds and bus widths, as well as customizable FIFO parameters.
The POS-PHY Level 3 function consists of two separate MegaCore products-the PHY layer (ordering code: PLSM-POSPHY/P3) and the Link layer (PLSM-POSPHY/L3). The Link layer core and the PHY layer core will be fully released by the fourth quarter, and both are priced at $12,995 each. For further information visit www.Altera.com.
Related News
- Altera Announces New Family of IP Cores Designed for PMC-Sierra's POS-PHY Solutions
- Xilinx and PMC-Sierra Announce Availability of Interoperable SPI-4.2/POS-PHY Level 4 Solution with Dynamic Alignment
- Altera and PMC-Sierra Introduce Multi-Serial Protocol Development System
- Altera and PMC-Sierra Extend High-Speed Serial Options for FPGAs and Structured ASICs
- Altera’s Stratix GX FPGA’s Embedded Dynamic Phase Alignment Simplifies Board Design with PMC-Sierra’s XENON Ethernet Devices
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Most Popular
E-mail This Article | Printer-Friendly Page |