Altera's Stratix II FPGAs Provide Complete Design Security Solution for Protection of Intellectual Property

Stratix II and Stratix II GX Devices are the Industry’s Only High-Density, High-Performance FPGAs with Non-Volatile Design Security Feature

San Jose, Calif., June 19, 2006  Intellectual property (IP) protection has become a primary challenge in today’s highly competitive commercial environment, as well as in government and military applications, which have an inherent need for elevated security. In response, Altera Corporation (NASDAQ:ALTR) today announced the availability of a comprehensive Stratix^® II FPGA design security solution to protect IP. The easy-to-implement Stratix II design security solution uses advanced encryption standard (AES) along with a 128-bit non-volatile key, and is ideal for applications requiring design flexibility and protection.

As FPGAs advance in density, functionality and performance with each new process generation, designers are increasingly using them to perform critical system functions that were traditionally filled by ASICs or ASSPs. The Stratix II design security solution offers benefits for a number of applications and market environments:

In areas where IP laws are not well enforced, the Stratix II design security feature enables IP protection, resulting in increased revenue retention.

• The Stratix II design security solution allows different security keys to be programmed into different Stratix II devices, enabling product version control and customization.

• The ability to encrypt configuration files in Stratix II FPGAs ensures royalty income for IP vendors, since they can track exact IP usage.

• The tampering protection of the Stratix II design security solution prevents undesired modification of gaming machines.

• The Stratix II design security solution allows military customers to protect core technology and information, and prevent tampering.

• ASSP vendors can test market and adapt the functionality in their ASSPs via Stratix II FPGAs while protecting their IP.

“The non-volatile security provided by Stratix II FPGAs, as well as HardCopy^® structured ASICs, allows us to deliver solutions that offer the security and cost effectiveness of ASSPs and the time-to-market and flexibility of programmable logic,” said Peter Viereck, CEO of TPACK. “Because Stratix II FPGAs combine AES with industry-leading performance and density, we can offer comprehensive Ethernet/MPLS and Ethernet-over-SONET/SDH solutions that meet the most rigorous requirements.”

Securing Your Devices With the AES Encryption Key

Stratix II and Stratix II GX devices are the industry’s first FPGAs to support configuration bitstream encryption using the 128-bit AES and a non-volatile key. Selected by the National Institute of Standards and Technology (NIST) and adopted by the U.S. government to protect sensitive information, AES is the most advanced encryption algorithm available today. A user-defined AES key can be programmed into the 128-bit non-volatile key stored in Stratix II devices. The same key is used by Quartus^® II design software to generate an encrypted configuration file stored in an external memory or configuration device. At power up, the memory or configuration device sends the encrypted configuration file to the FPGA and the device then uses the stored key to decrypt the file and configure itself. This Stratix II AES implementation is FIPS‑197 certified.A comprehensive design security solution for Stratix II GX will be available in the third quarter of 2006.

Designers can easily implement the design security solution, which includes application notes and various on-board and off-board key programming methods, to suit different manufacturing flows. They can select from an EthernetBlaster cable, JTAG Technologies’ (www.jtag.com) in-system programming tools, System General’s (www.sg.com.tw) socket programming equipments, in-circuit testers and key programming services offered by major Altera distributors.

“Stratix II series FPGAs are the industry’s only high-performance FPGAs supporting non-volatile design security,” said David Greenfield, Altera’s senior director of product marketing for high-end FPGAs. “Stratix II FPGAs deliver a secure approach that protects proprietary designs and IP using bitstream encryption, providing clear differentiation for customers looking to protect their IP investment.”

To register for Altera’s “How to Protect Your IP Using FPGA Design Security” net seminar, visit www.altera.com/netseminar_st2security.

For more information about the Stratix II design security feature, visit www.altera.com/st2-security.  For more information on how to use the Stratix II design security feature, contact your local Altera sales representatives, www.altera.com/corporate/contact/con-index.html. For more information about Stratix II devices, visit www.altera.com/stratix2. For more information about Stratix II GX devices, visit www.altera.com/stratix2gx.

About Altera

Altera’s programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more at www.altera.com.

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