Digital Core Design announces the release of a new DoCD kit v2.0 evaluation board
The DoCD kit v2.0 is a modern evaluation board with DCD on-Chip Debugger system which allows quick and effective testing HDL projects based on DCD IP cores. The Evaluation board bases on Altera's Stratix II (EP2S16) FPGA device. An environment of FPGA chip make among other:
- SRAM ( 1M x 32b ),
- FLASH ( 4M x 32b )
- DDR SDRAM ( 4 x (64M x 8b)) memories,
- I2C interface with implemented RTC ( DS1629 ) and EEPROM ( 24FC515)
- SPI interface with implemented DataFlash ( AT45DBI61BM )
- Two PS/2 sockets,
- Compact Flash socket
- UART (1Mbps),
- 1-Wire interface
- Five clocks with PLLs (software application controlled)
- Voltage, current and temperature measuring.
This development board connected with DCD on-chip Debugger system makes powerful tool which makes easy way to implement, testing and debugging DCD microcontrollers into real FPGA device and significantly reduces time of designing phase
For more information please see DCD web site.
About Digital Core Design
DCD is a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house, an expert in IP cores architecture improvements. DCD sells its products and services directly and through its global distribution network. DCD offers VHDL and Verilog high performance and synthesizable IP cores for a speed optimized 8-, 16- and 32-bit processors, peripherals, serial interfaces, floating point arithmetic units and coprocessors. The functionality of IP solutions offered by DCD were up to date appreciated by over 200 licenses sold to over 150 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, MAXIM, RAYTHEON, OSRAM, GENERAL ELECTRIC, FARADAY, SAGEM, FLEXTRONICS and GOODRICH. DCD also became a member of first-class branch partner programs like: AMPP of ALTERA, AllianceCORE of XILINX, ispLeverCORE Connection of LATTICE and IP Catalyst of SYNOPSYS. For more information, please visit: www.dcd.pl.
|
Digital Core Design Hot IP
Related News
- ChipX Simplifies DDR2 Design With Industry Standard DDR PHY Interface v2.0
- CSR brings Bluetooth v2.0 with EDR to austriamicrosystems' Mobile Entertainment platform for MP3 Players
- SafeNet Demonstrates Interoperability with Leading Device Manufacturers at First OMA DRM V2.0 Test Fest
- Broadcom retasks SoC for Docsis v2.0 duties
- Verisity Upgrades AHB e Verification Component; AHB e Verification Component v2.0 Adds eRM Compliance, Plus Multi-Layer and AHB-Lite Support
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |