Digital Core Design announces the release of a new DoCD kit v2.0 evaluation board
The DoCD kit v2.0 is a modern evaluation board with DCD on-Chip Debugger system which allows quick and effective testing HDL projects based on DCD IP cores. The Evaluation board bases on Altera's Stratix II (EP2S16) FPGA device. An environment of FPGA chip make among other:
- SRAM ( 1M x 32b ),
- FLASH ( 4M x 32b )
- DDR SDRAM ( 4 x (64M x 8b)) memories,
- I2C interface with implemented RTC ( DS1629 ) and EEPROM ( 24FC515)
- SPI interface with implemented DataFlash ( AT45DBI61BM )
- Two PS/2 sockets,
- Compact Flash socket
- UART (1Mbps),
- 1-Wire interface
- Five clocks with PLLs (software application controlled)
- Voltage, current and temperature measuring.
This development board connected with DCD on-chip Debugger system makes powerful tool which makes easy way to implement, testing and debugging DCD microcontrollers into real FPGA device and significantly reduces time of designing phase
For more information please see DCD web site.
About Digital Core Design
DCD is a private Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house, an expert in IP cores architecture improvements. DCD sells its products and services directly and through its global distribution network. DCD offers VHDL and Verilog high performance and synthesizable IP cores for a speed optimized 8-, 16- and 32-bit processors, peripherals, serial interfaces, floating point arithmetic units and coprocessors. The functionality of IP solutions offered by DCD were up to date appreciated by over 200 licenses sold to over 150 customers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, MAXIM, RAYTHEON, OSRAM, GENERAL ELECTRIC, FARADAY, SAGEM, FLEXTRONICS and GOODRICH. DCD also became a member of first-class branch partner programs like: AMPP of ALTERA, AllianceCORE of XILINX, ispLeverCORE Connection of LATTICE and IP Catalyst of SYNOPSYS. For more information, please visit: www.dcd.pl.
|
Digital Core Design Hot IP
Related News
- ChipX Simplifies DDR2 Design With Industry Standard DDR PHY Interface v2.0
- CSR brings Bluetooth v2.0 with EDR to austriamicrosystems' Mobile Entertainment platform for MP3 Players
- SafeNet Demonstrates Interoperability with Leading Device Manufacturers at First OMA DRM V2.0 Test Fest
- Broadcom retasks SoC for Docsis v2.0 duties
- Verisity Upgrades AHB e Verification Component; AHB e Verification Component v2.0 Adds eRM Compliance, Plus Multi-Layer and AHB-Lite Support
Breaking News
- RISC-V in Space Workshop 2025 in Gothenburg
- VeriSilicon introduces AcuityPercept: an AI-powered automatic ISP tuning system
- Avant Technology Partners with COSEDA Technologies to Enhance System-Level Software Solutions
- intoPIX Powers Ikegami's New IPX-100 with JPEG XS for Seamless & Low-Latency IP Production
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
Most Popular
- Qualcomm initiates global anti-trust complaint about Arm
- Sarcina Technology launches AI platform to enable cost-effective customizable AI packaging solutions
- EnSilica Agrees $18m 7 Year Design and Supply ASIC Contract
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Tower Semiconductor and Alcyon Photonics Announce Collaboration to Accelerate Integrated Photonics Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |