Tenison Delivers System Level Use Of IP With VTRAC Technology

Industry-Standard Interfaces Operate At Multiple Levels of Abstraction

San Jose Calif. – July 10, 2006 – Tenison Design Automation, a company focused on delivering tools that remove barriers to the adoption of system level design flows, has announced the release of its breakthrough product − VTRAC Technology. This addition to Tenison’s VTOC tool suite is a result of an OEM agreement with SpiraTech (see November 15, 2005 press release, Tenison-SpiraTech to Provide ESL Solution). VTRAC Technology is a library of industry-standard interface transactors that enable the rapid integration of new and legacy intellectual property (IP) blocks within system level modeling environments. It connects IP in system-on-chip (SoC) models, at any abstraction level from Register Transfer Logic (RTL) up to transactional Programmer’s View (PV).

The technology is combined with Tenison’s existing VTOC product – which generates SystemC or C++ models from HDL RTL – to facilitate the reuse of existing IP within system level designs. VTRAC Technology transactors are generated automatically from a formal specification of standard interface protocols, eliminating the need for hand coding by design teams. The transactors convert between all levels of abstraction for each interface and notify the end-user if protocol violations occur. Interface standards include AMBA2 AHB and APB, AMBA3 AXI, OCP-IP, and PCI Express, as well as other protocols. The technology has been deployed and tested in leading system level behavioral modeling environments such as ARM’s RealView SoC Designer, CoWare’s Platform Architect, and the OSCI SystemC reference simulator.

“The demand to incorporate legacy RTL simulation models in ESL design environments is increasing with the rapid adoption of system-level design as standard engineering practice. In many cases, the need to perform architectural analysis of a complete SoC requires significant import of bus and peripheral IP models,” commented Christopher Lennard, ESL Strategic Marketing at ARM. “By using Tenison’s VTOC to convert peripheral models from RTL into cycle-callable C models, a design team can use VTRAC to quickly create plug-and-play transaction-level SystemC models that comply with the ARM RealView ESL APIs. This provides a rapid path to model import into the ARM RealView SoC Designer tool, and any other environment complying with the open RealView ESL API specifications.”

Speeds System Simulation and Debug

The embedded system design challenge is to fit as much functionality as possible onto silicon and to achieve faster time-to-market, especially in consumer electronics, which has driven the need for VTRAC Technology. Within embedded systems, SoCs are a mix of new, reused, and third party IP, from disparate vendors and at various levels of abstraction. Linking this IP and integrating it within design environments, while increasing system level modeling performance, are critical factors for first-pass SoC design success. The technology allows design teams to deliver and use IP in a format suitable for system level modeling at any abstraction level.

“Until now, engineers have faced the arduous task of hand-coding their own transactors,” stated Dr Jeremy Bennett, Chief Technology Officer, Tenison Design Automation. “Typically, such labors have been one-off efforts yielding transactors with limited protocol compliance, which were rarely reusable by the design team let alone third parties. Tenison’s VTRAC Technology provides designers with a consistent source of transactor functionality offering full protocol compliance for a wide range of standard interfaces.”

To use VTRAC Technology, designers simply import an IP block that has been converted to SystemC or C++ using VTOC, along with the appropriate transactor. Then, using the system-level design environment’s existing user interface and tools (for example RealView SoC Designer or CoWare Platform Architect), the designer makes connections between the VTOC/VTRAC model and other transaction-level models within the SoC.

VTRAC Technology speeds system verification and debug when combined with VTOC’s ability to generate C++ models of RTL IP. The designer gains multi-level visibility of the various models in the SoC behavioral model while VTRAC Technology detects any non-conformance to the communication protocol standard. It also detects quiescence within buses of the model, allowing the elimination of unnecessary computational effort and hence leading to increased SoC modeling performance.

“SoC design is becoming an IP assembly task,” stated Martin Harding, President and CEO of Tenison Design Automation. “However, the lack of high level models and the interfaces for integrating IP from different sources at various levels of abstraction has hindered the application of ESL methodologies for SoC design. We’ve now effectively solved these problems with the integration of Tenison’s VTOC and VTRAC Technology.”

Availability and Price

VTRAC Technology is being used in leading customer sites and is commercially available now. For more information, contact Tenison at sales@tenison.com.

About Tenison

Tenison products provide the cornerstone for bridging the Model Gap in ESL design. Its products span from ‘concept-todelivery’ for synthesizing RTL into models at higher levels of abstraction for system level design. Customers include ARM, Conexant Systems, Renesas, Ricoh, Samsung, ST Microelectronics, and other Fortune 100 companies. For more information, please visit www.tenison.com.