Celoxica Adds Floating-Point Toolkit to IP Portfolio; Cores Optimized for FPGA-Based Digital Signal Processing & High-Performance Computing Applications
OXFORDSHIRE, England--July 19, 2006--Celoxica (AIM:CXA) today announced availability of a toolkit for Floating-Point arithmetic implementation in high-density programmable logic. The IEEE 754 compliant libraries support single, double and custom precision Floating-Point. They are fully parameterizable for area, latency and performance optimization across all leading programmable logic architectures and can be tuned to specific application requirements delivering industry-leading performance and unrivalled flexibility.
Developed in conjunction with the Institute of Information Theory and Automation (UTIA) in the Czech Republic, the underlying IP behind the Floating-Point ToolKit represents the first milestone between Celoxica and UTIA since the two organizations signed a multi-year research agreement. The Floating Point ToolKit is being deployed into high-performance computing (HPC) application areas such as the automated trading of equities and related financial derivatives, oil and gas exploration and embedded applications including audio and video DSP filtering.
Parallel designs using the Floating-Point core modules can deliver up to 50 Giga Floating-Point Operations per Second (GFLOPS) and support the processing requirements in real-time imaging and signal processing applications, and compute-intensive routines typically used in clustered server and supercomputer architectures. By exploiting the inherent parallelism of FPGA hardware, exceptionally high Floating-Point arithmetic can be achieved with significant performance-per-watt energy savings. The combination of the Floating-Point ToolKit with programmable logic means the number of instances of the Floating-Point operator is user configurable and scalable.
The Floating-Point ToolKit supports pipelined add, subtract, multiply, divide and square-root operations, and conversions to and from 32bit fixed point. The add module has a five stage pipeline for all precisions and the multiply module is provided with user configurable pipelines to support the embedded multiplier and DSP blocks in modern FPGA devices. 18m12, 24m16, 32m24, 40m32, 64m53 precisions are supported as is IEEE754 rounding to the nearest and even. The custom precisions provided in the ToolKit are optimized for designers who want to take maximum advantage of embedded FPGA resources such as DSP blocks and make optimum use of existing gate counts.
For simulation and verification the ToolKit supports processor-in-the-loop and hardware-in-the-loop simulation. Bit-exact Simulink blocks for all arithmetic operations supported by the library (precisions 18m12, 24m16, 32m24, 40m32 and 64m53) are included and test vectors can be created in Simulink models and debugged in Celoxica's DK Design Suite. Breakpoints help debug the implementation at the register level and DK's simulator reads data generated in the Simulink model and returns data back for verification of the bit exact results. Implementation to the FPGA is supported with API layers that allow application reuse across different programmable platforms without additional development or recoding.
"This important addition to our IP portfolio addresses customer need in both the DSP and HPC space for a very high-performance, fully parameterizable and platform-independent floating-point capability," said Chris Sullivan, director of strategic marketing for Celoxica. "We can readily tune and re-tune the libraries to meet changing architectures and specifications, and the current implementation not only provides industry-beating performance and flexibility, but the libraries themselves demonstrate the extreme circuit optimization that can be achieved using the DK Design Suite."
The ToolKit is available from Celoxica in a variety of different configurations. For further information contact info@celoxica.com or your local Celoxica sales office.
About Celoxica
A leader in electronic system level design (ESL), Celoxica is enabling the next generation of advanced electronic products by producing tools, boards, IP and services that turn software into silicon. Celoxica technology raises design abstraction to the algorithm level, accelerating productivity and lowering risk and costs by generating semiconductor hardware directly from C-based software descriptions. Adding to a growing installed base, Celoxica provides the world's most widely used C-based behavioral design and synthesis solutions to companies developing semiconductor products in markets such as consumer electronics, defense and aerospace, automotive, industrial and security. Celoxica is a publicly traded company on the Alternative Investment Market of the London Stock Exchange under the symbol CXA. For more information, visit: www.celoxica.com.
|
Related News
- Altera First to Benchmark Complex High-Performance Floating-Point Digital Signal Processing Designs on 28 nm FPGAs
- Actel Offers High-Performance, Easy-to-Use FPGA-Based DSP Solution
- Cortus Announces FPS6 32 bit Floating Point Microcontroller IP Core for High Performance Control and Signal Processing Applications
- Coreworks introduces SideWorks, a high-performance, small footprint and ultra low power licensable Digital Signal Processing (DSP) Core
- Xilinx Targets $2 Billion High-Performance DSP Market With FPGA Industry's First Application-Optimized Solution Roadmaps
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |