Virage Logic's ASAP Memory Solidifies Place in the SoC Ecosystem with Incorporation into CEVA DSP Platform
High-Speed, High-Performance Memories Accelerate Silicon Success of DSPs for High-Volume Consumer and Communications Applications
SAN FRANCISCO -- July 24, 2006-- Virage Logic Corporation (Nasdaq:VIRL), a pioneer in Silicon Aware IP(TM) and leading provider of semiconductor intellectual property (IP) platforms, and CEVA, Inc. (Nasdaq:CEVA) (LSE:CVA), the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry, announced today that Virage Logic's Area, Speed and Power (ASAP) Memory(TM) High-Speed (HS) memory IP has been adopted by CEVA for global use in its CEVA-XS(TM) based system platforms
Virage Logic's ASAP Memory HS is designed for high-performance applications, making it the perfect choice for the CEVA-XS platforms, including the CEVA-XS1200, which targets mobile multimedia applications such as high-end multimedia phones, personal media players (PMPs) and mobile TVs, and the CEVA-XS1102, which targets 3.5G/HSDPA handsets, WiMax/WiBro terminals and Smartphone applications. CEVA-XS is a family of low-power, highly integrated DSP system platforms designed to reduce development costs and time-to-market for customers designing next-generation DSP-powered devices. Built around the industry-leading CEVA-X DSP cores, the CEVA-XS platforms use industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip.The ASAP Memory HS's high-performance architecture begins with the design of its bit cells, which are optimized for fast signal propagation, with the lowest possible bit-line coupling for very high stability. Proprietary circuit design techniques, including high-speed sense amplifiers, fast clocking and fast bit-line recovery contribute to achieving the high speeds required by today's high-performance applications.
"Virage Logic's highly differentiated IP was chosen for its ability to help us maximize the performance of our CEVA-XS DSP Platforms," said David Dahan, vice president of operations at CEVA. "In turn, these performance advantages provide our customers with the ability to differentiate their products that target the multimedia, communications and consumer markets."
"CEVA's decision to incorporate Virage Logic's ASAP Memory IP into their CEVA-XS system platforms underscores the speed and performance benefits that choosing the right physical IP provides to the overall performance of functional IP such as DSPs," said Jim Ensell, senior vice president of marketing and business development for Virage Logic. "We're very pleased to serve as CEVA's trusted IP partner."
Increasingly complex System-on-Chips (SoCs) require greater amounts of memory, which present significant wafer yield issues. Using Virage Logic's silicon-proven embedded memory IP, designers can integrate small, moderate or large amounts of on-chip memory to reduce overall system cost and size, while meeting time-to-market requirements. The ASAP Memory HS product is suited for high-volume applications where high-speed, area-efficient memory implementation is a requirement.
About Virage Logic's ASAP Memory Product Line
Today's System-on-Chip (SoC) designs vary widely with respect to their density, speed and power requirements. To address these demanding requirements, Virage Logic has architected three separate families of sub-megabit embedded memory compilers under the Area, Speed and Power (ASAP) Memory product line. The High-Density (HD) memories address the needs of many applications that are optimized for area: the High-Speed (HS) memories address the requirements of high-performance systems and the Ultra-Low Power (ULP) memories address the needs of power-sensitive portable applications. All ASAP memories can optionally include the comprehensive Built-In-Self-Test (BIST) implementation found in Virage Logic's Self-Test and Repair (STAR) Memory System(TM) or integrate with most third-party BIST engines.
The Virage Logic ASAP Memory product line represents the largest selection of silicon-proven, high quality, easy to integrate, embedded memory IP available today. Hundreds of memory compilers are available ranging from 0.25um to 65nm and spanning many foundries.
About CEVA, Inc.
Headquartered in San Jose, Calif., CEVA is the leading licensor of digital signal processor (DSP) cores, multimedia and storage platforms to the semiconductor industry. CEVA licenses a family of programmable DSP cores, associated SoC system platforms and a portfolio of application platforms including multimedia, audio, Voice over Packet (VoP), Serial Attached SCSI (SAS) and Serial ATA (SATA). In 2005, CEVA's IP was shipped in over 130 million devices. For more information, visit http://www.ceva-dsp.com
About Virage Logic Corporation
Founded in 1996, Virage Logic Corporation (Nasdaq:VIRL) rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Now, as the company celebrates its 10th anniversary, it is a global leader in semiconductor IP platforms comprising embedded memories, logic, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP(TM). Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company uses its FirstPass-Silicon(TM) Characterization Lab for certain products to help ensure high quality, reliable IP across a wide range of foundries and process technologies. The company also prides itself on providing superior customer support and was recently named Customer Service Leader of the Year in the Semiconductor IP Market by Frost & Sullivan. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.
|
Related News
- Virage Logic's High-Density ASAP Memory(TM) IP Used in Development of Low-leakage Wireless Multimedia Processors From NVIDIA
- Virage Logic's Shared memory System Increases SoC performance
- Novatek Adopts CEVA's Latest Sensor Hub DSP for New Multi-sensor IP Camera SoC
- CEVA's High-Performance DSP Solution to Power Renesas' Next-Generation Automotive SoC
- CEVA Announces Silicon-based Platform to Streamline Development of Low-Power 'Smart and Connected' Devices
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |