English
Poseidon Announces the Second Generation of Hardware Accelerator Synthesis for Processor-Based Designs
Poseidon's ESL tools enabled 14X acceleration with 2 man-weeks effort for YUV2RGB-conversion algorithm
San Jose, CA – July 25, 2006 – Poseidon Design Systems today announced the release of the second generation Triton Builder tool. This enhancement supports the generation of a fully pipelined hardware accelerator to increase the performance of Poseidon’s automated solutions by an additional 3-10X over our existing market leading technology. With this solution designers can easily get between 10-450X performance increases from standard ANSI C algorithms. This new performance capability enables a whole new class of video, multimedia and imaging applications to be implemented with embedded processor architectures, thereby increasing flexibility and decreasing time to market.
Poseidon will be showing a demonstration of a color conversion and DCT applications at the 2006 Design Automation Conference. This application was generated using the Triton Tuner and Builder tool suite with just 2 man weeks of effort. The resultant solution is implemented on a Virtex 4 platform using the PowerPC core from Xilinx and exhibits a 14X performance increase over the software running on the processor.
Poseidon’s Triton tool suite is comprised of two tools, Tuner and Builder, which provides the designer with the ability to fully develop an efficient processor-based architecture. Poseidon’s Tuner tool offers hardware and software architects an easy to use SystemC simulation environment to quickly analyze and optimize complex software, architectures and systems. With the Builder Tool, time critical algorithms can also be partitioned and migrated from software into dedicated hardware solutions with an efficient hardware accelerator. Through hardware acceleration significant increases in performance can be obtained along with reductions in power and development time. With Poseidon Triton tools designers can tradeoff Performance, power and cost. These tools support ARM, PowerPC, MicroBlaze and Nios II architectures on ASIC and FPGA platforms. The solutions are optimized for video, VoIP, audio, imaging, wireless, networking, and security devices.
About Poseidon Design Systems
Poseidon is an Electronic Design Automation and Service company with offices in Atlanta, GA., San Jose, CA, and Bangalore, India. Founded in July 2002, Poseidon provides products and services for modeling and designing processor-based SoCs. Poseidon's Electronic System Level tools allow users to rapidly analyze, optimize and accelerate a complete SoC system. For additional information about Poseidon Design Systems, visit www.poseidon-systems.com.
San Jose, CA – July 25, 2006 – Poseidon Design Systems today announced the release of the second generation Triton Builder tool. This enhancement supports the generation of a fully pipelined hardware accelerator to increase the performance of Poseidon’s automated solutions by an additional 3-10X over our existing market leading technology. With this solution designers can easily get between 10-450X performance increases from standard ANSI C algorithms. This new performance capability enables a whole new class of video, multimedia and imaging applications to be implemented with embedded processor architectures, thereby increasing flexibility and decreasing time to market.
Poseidon will be showing a demonstration of a color conversion and DCT applications at the 2006 Design Automation Conference. This application was generated using the Triton Tuner and Builder tool suite with just 2 man weeks of effort. The resultant solution is implemented on a Virtex 4 platform using the PowerPC core from Xilinx and exhibits a 14X performance increase over the software running on the processor.
Poseidon’s Triton tool suite is comprised of two tools, Tuner and Builder, which provides the designer with the ability to fully develop an efficient processor-based architecture. Poseidon’s Tuner tool offers hardware and software architects an easy to use SystemC simulation environment to quickly analyze and optimize complex software, architectures and systems. With the Builder Tool, time critical algorithms can also be partitioned and migrated from software into dedicated hardware solutions with an efficient hardware accelerator. Through hardware acceleration significant increases in performance can be obtained along with reductions in power and development time. With Poseidon Triton tools designers can tradeoff Performance, power and cost. These tools support ARM, PowerPC, MicroBlaze and Nios II architectures on ASIC and FPGA platforms. The solutions are optimized for video, VoIP, audio, imaging, wireless, networking, and security devices.
About Poseidon Design Systems
Poseidon is an Electronic Design Automation and Service company with offices in Atlanta, GA., San Jose, CA, and Bangalore, India. Founded in July 2002, Poseidon provides products and services for modeling and designing processor-based SoCs. Poseidon's Electronic System Level tools allow users to rapidly analyze, optimize and accelerate a complete SoC system. For additional information about Poseidon Design Systems, visit www.poseidon-systems.com.
|
||||||
Related News
- CoWare Announces Software Development Solution for ARM Cortex-A5 and ARM Cortex-M4 Processor-Based Designs
- Synopsys Enables Optimized High-Performance Energy-Efficient ARM Processor-based Designs
- Cadence and ARM Deliver Innovative Kit to Speed Verification Closure for ARM Processor-Based Designs
- Altera Announces New Tool for Easily Accelerating C Into Hardware for Nios II Processor-Based Systems
- Novas Extends Industry-Standard Debug Platform for Embedded Processor-Based System-on-Chip Designs
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |