Cadence Introduces Universal Verification Components; First Verification-Plan-Enabled Verification IP Integrates Compliance Management and Mixed Language Support

SAN JOSE, Calif. -- August 7, 2006 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today introduced Universal Verification Components (UVCs), a new line of reusable verification IP (VIP) that integrates compliance management and mixed-language flexibility with advanced simulation-based testbench technology. UVCs, part of Cadence's strategy to deliver VIP that spans the entire verification process, maximize quality, predictability and efficiency, while minimizing schedule delay risks and the need for specific protocol expertise. This enables customer to focus on their core business values—maximizing design differentiation and product quality.

The new Cadence® verification component IP includes a unique executable verification plan (vPlan) that drives management of the verification process and automatically calibrates, measures and reports on protocol compliance. In addition, UVCs are the industry's only VIP that supports all standard languages backed by the IEEE, including SystemVerilog and "e" for test benches, and SystemC, VHDL, and SystemVerilog for design.

"Verifying our device's interfaces are demanding and complex," said Russell David, vice president of engineering at Clearspeed. "We selected the Cadence vPlan and have been pleased with the support and positive experience our team has had by working with Cadence."

Cadence will provide UVCs for the protocols most in demand by customers including ARM's AMBA AHB and AXI, PCI Express, Ethernet and USB. UVCs expand the existing Cadence portfolio of testbench verification IP. Each UVC is pre-verified against the protocol specifications and is based on the industry-proven Cadence Plan-to-Closure Methodology for plug-and-play adoption. Users employing this latest generation of VIP will gain access to its underlying integrated methodology that dramatically shortens bring-up and simplifies reuse of their verification environments at the block, chip and system levels. With this mix of powerful technology, methodology, and process automation-based capabilities, UVCs will provide a robust multi-language solution offering benefits for every design or verification specialist.

"As design and verification challenges continue to grow, YOGITECH is increasingly asked to share its deep expertise and verification IP to improve our customers' productivity and the predictability of their verification processes," said Silvano Motto, CEO of YOGITECH. "As a long-time Cadence Verification Alliance partner, and provider of Incisive® verification IP, we clearly see the value that vPlan-enabled UVCs will bring to our customers as they strive for protocol compliance and verification closure."

"We've seen tremendous success from thousands of customer projects using our pre-verified verification components," said Steve Glaser, corporate vice president of the Cadence Verification Division. "We're leveraging our proven expertise to deliver the next generation of multi-language universal verification components to bring our customers from plan to verification closure faster than ever."

UVCs are already in customer use today and will become more broadly available in Q3'2006.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.