Kawasaki Microelectronics, Inc. Selects CoWare Platform Architect for Next Generation SoC Designs
CoWare's Platform-Driven ESL Design Solution Provides Optimal Architecture for Kawasaki's ASIC Customers and Dramatically Shortens Turnaround Time
SAN JOSE, Calif.--Aug. 21, 2006--CoWare® Inc., the leading supplier of platform-driven electronic system-level (ESL) design software and services, announced that Kawasaki Microelectronics, Inc. (K-Micro), Chiba, Japan, selected CoWare Platform Architect and services for the design of its next generation multi-function printer system-on-chip (SoC). CoWare Platform Architect will provide K-Micro with the optimal architecture for its ASIC customers, which will dramatically reduce turnaround time. All K-Micro's customers have individual requirements and require unique ASICs. The flexibility of the tools will enable K-Micro to provide optimized solutions beyond multi-function printers as well, and K-Micro will expand this technology into the communications equipment industry. A platform-based design technology will enable K-Micro to provide the optimal ASIC architecture for each customer design. This platform-based design methodology will give K-Micro and their customers an important competitive advantage. Prior to Platform Architect, K-Micro had been using a traditional architecture exploration methodology that required a great deal of engineering time, yet did not produce an optimal architecture.
"We needed to create an efficient methodology to optimize the architecture for our SoC ASICs based on the MIPS processor and Sonics interconnects," said Kyoichi Kissei, executive vice-president, Kawasaki Microelectronics, Ltd. "CoWare Platform Architect was the only ESL design tool on the market that provided SystemC models for those interconnects in addition to an extremely powerful analysis capability. It was an easy decision to go with CoWare."
"K-Micro and our other customers are very interested in our new Virtual Platform ESL design solution for their new product designs because it will provide them the broadest system design solution on the market," said A.K. Kalekos, vice-president marketing and business development, CoWare. "CoWare is one of the only platform-driven ESL providers to use SystemC, which has become the industry standard for system design. In addition, CoWare is the only company with a complete platform-based ESL design solution for hardware architecture exploration and validation, and device software development, which is very attractive to a growing number of systems companies faced with increasingly complex designs."
About CoWare
CoWare is the leading supplier of platform-driven electronic system-level (ESL) design software and services. CoWare offers a comprehensive set of ESL tools that enable electronics companies to "differentiate by design" through the creation of system IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; hardware/software co-design; and virtual platforms for device software development. The company's solutions are based on open industry standards including SystemC. CoWare's customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge. CoWare's corporate investors include ARM (LSE:ARM - News; Nasdaq:ARMHY - News), Cadence Design Systems (NASDAQ:CDNS - News), STMicroelectronics (NYSE:STM - News), and Sony Corporation (NYSE:SNE - News). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services visit http://www.coware.com.
|
Related News
- Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs
- Synopsys to Enable New Levels of Insight into SoC Designs and Systems with Industry's First Silicon Lifecycle Management Platform
- Synopsys Delivers Platform Architect Ultra to Enable the Next Wave of AI SoCs
- NetSpeed launches SoCBuilder - AI-powered design and integration platform to accelerate SoC designs
- Arm Physical IP to Accelerate Mainstream Mobile and IoT SoC Designs on TSMC 22nm ULP/ULL Platform
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |