DDR PHY Interface Specification to be Unveiled Next Week at MemCon

ARM, Denali, Intel, Rambus, Samsung, and Synopsys team on specification to address development challenges for DDR-DRAM memory systems

PALO ALTO, Calif. -- Sept. 6, 2006 -- Denali Software, Inc., today announced plans to host the unveiling of the DDR PHY Interface (DFI) specification during its MemCon event next week at the Santa Clara Convention Center. The specification is the result of a collaborative effort by industry leaders to describe a common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs.

Event: MemCon San Jose

Session: "An Introduction to the DDR PHY Interface (DFI) Specification"

When: 3:40PM PST, Wednesday, September 13, 2006

Where: Santa Clara Convention Center, Santa Clara, California

Details: Free registration for industry professionals at: http://www.memcon.com

"The resources needed to integrate and verify the memory controller logic and PHY designs from third-party vendors represent a significant cost to all parties involved," said Bryan Jones, IP outsourcing program manager, Mobility Group LTG/DAC for Intel Corporation. "From a systems perspective, it was essentially defeating the value proposition for outsourcing this type of design IP. We now have a motivated team of experts in this field, pulling together to develop a common specification that will benefit us all."

The memory controller logic and PHY interface represent the two primary design elements in DDR-DRAM memory systems, which are used in virtually all electronic system designs, from cell phones and set-top boxes, to computers and network routers. These two components of the memory system require a uniquely different set of engineering skills, tools and methodologies, and thus, are often developed by separate engineering teams, or are acquired from different third-party design intellectual property (IP) vendors. Consequently, the lack of a standard interface between the two design elements has become the source of significant integration and verification costs by systems developers, memory controller vendors, and PHY providers.

"The collaborative efforts toward a standard PHY interface, that provides a common high-speed DDR PHY solution for added convenience in the interface with various memory controllers, will support ASIC suppliers and customers to maximize development efficiency by reducing both design resources and verification costs," said Steve Park, vice president of ASIC and Foundry Engineering at Samsung Electronics' System LSI Division.

The goal of the DFI specification is to define a common interface between the memory controller logic and the PHY interface in order to reduce cost, time-to-market, and increase the potential for reuse of the individual components that make up the memory system. The DFI specification is being developed by expert contributors from recognized leaders in the semiconductor, IP and electronic design automation (EDA) industries, including: ARM, Denali, Intel, Rambus, Samsung, and Synopsys.

"The DFI specification simplifies memory design by offering customers a common starting point for integrating multi-vendor IP," said Rich Warmke, director of marketing for Platform Solutions at Rambus. "We remain committed to enabling the easy and rapid integration of Rambus PHYs and digital cores to allow customers the continued benefit of the unique value-added features and patented innovations Rambus memory solutions bring to the market."

"Synopsys is encouraged by the formation of the DFI committee and looks forward to working with some of the industry's most recognized leaders in the DDR2 SDRAM memory ecosystem," said Guri Stark, vice president of marketing for the Solutions Group at Synopsys. "This standard will help our customers implement high performance memory interface solutions reliably and efficiently. The goals and efforts of the DFI committee are focused on resolving key customer challenges of selecting, integrating, and implementing high performance DDR2 interfaces."

"ARM is a strong advocate of industry standards and looks forward to supporting the DFI initiative as a founding member," said Herb Gebhart, director of product marketing, Physical IP at ARM.

"We are very pleased with the quality of the participants in this effort," said Brian Gardner, vice president of IP products at Denali. "These companies truly represent the best minds in the field, and their contributions to this important industry issue will bear fruit for years to come."

About the DFI Specification

The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices.

About Denali Software

Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND and DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com .