IntellaSys Offers Free Download of T18 Compiler/Simulator for SEAforth Multicore Processors Targeting Embedded Applications
CUPERTINO, Calif.-- October 09, 2006 --IntellaSys Corporation today announced the availability of a freshly minted compiler/simulator to support its recently introduced SEAforth™ multicore processors for embedded applications. The novel T18 compiler/simulator, which is now available to registered users as a free download on the company’s web site (www.intellasys.net), leverages fully the efficiencies inherent in the company’s VentureForth™ software. The T18 will be publicly demonstrated for the first time tomorrow during In-Stat’s Fall Processor Forum exhibition, scheduled to run from 5:30 to 8:30 p.m. at the Doubletree Hotel in San Jose, California.
“As a key development tool for our SEAforth family of multicore processors, our T18 facilitates the design of embedded solutions that exploit the performance-per-watt benefits of our Scalable Embedded Array™ (SEA) platform,” said Chet Brown, president and CEO of IntellaSys. ”Our T18 can be used to view a compelling simulation of how we deploy a test crawler to completely tour all 24 cores on a single chip and rapidly perform extensive processing on each.”
Brown noted that testing multicore solutions requires new approaches to high-speed testing, and that the crawler technique is just one of the methods his firm is using to validate the performance of SEAforth multicore devices. The simulated crawler program is included with the free download of the T18 so that registered users can immediately operate the simulator without having to write their own program.
SEAforth Multicore Processors
Formally launched earlier this year, the SEAforth family of multicore solutions employs an innovative dual-stack architecture that is both asynchronous and scalable. The on-chip benefits of initial SEAforth chips coming to market include:
- RAM and ROM on each core (64 words each) to break the memory bottleneck
- Flash memory interface to ripple-load application code into cores at boot
- Static/dynamic RAM interface to facilitate common data memory access
- Real-time clock support
- 18-bit A/D and 9-bit D/A converters to eliminate need for external data conversion
- Serial (SPI) ports, which can double as I2C and I2S ports
- Extensive parallel I/O lines for versatile “bit banging”
- Scalable connectivity among multiple SEAforth-24 chips via high-speed I/O ports
Forthlet™ Code Library
Extending the power of the company’s VentureForth software (RISC derivative of Forth) is the Forthlet Code Library. Unlike conventional code libraries that require linking the entire library into the applications program if just one routine is used, the Forthlet Library links only the routines used. In this system, there is no penalty for building a large, comprehensive library. Routines in the Forthlet Code Library take the form of Forthlet code objects that can be moved around the chip from core to core to do special processing. Forthlets are the basic building blocks of code on the SEA Platform. They are used in the ROM BIOS in each core, and in the library of pre-coded functions. Even the user written program takes the form of a large Forthlet code object that calls the others.
About IntellaSys
IntellaSys Corporation is a TPL Group Enterprise focused on developing distributed digital media semiconductor solutions including SEAforth multi-core processors, OnSpec USB memory controllers and Indigita content secure connectivity devices. With headquarters in Cupertino, California, IntellaSys operates seven design centers, three of which are in California as well as four others based in Tempe, Arizona; Castle Rock, Colorado; Cincinnati, Ohio; and Vienna, Austria. The TPL Group, founded in 1988, specializes in the development, commercialization and management of IP assets. For more information, visit www.intellasys.net.
|
Related News
- EEMBC Launches Embedded Industry's First Floating-Point Benchmark Suite Targeting Microcontrollers to High-End Multicore Processors
- ARM Offers Free Access to Cortex-M0 Processor IP to Streamline Embedded SoC Design
- Mentor Graphics Hypervisor Delivers High Performance and Security for Multicore Processors and Enables Multi-OS Consolidation
- IntellaSys Unveils Revolutionary ''Scalable Embedded Array(TM) (SEA) Platform'' to Launch Multicore Processor Chip Solutions
- Logic Design Solutions launches a new version of its NVMe HOST IP Targeting embedded recorder systems
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |