Semiconductor Memories and MEMS Serve as Potential 'Killer' Applications for SOI

PALO ALTO, Calif., Oct. 31, 2006 -- Silicon-On-Insulator (SOI) has become the core material for high-end microprocessors and other cutting-edge chips. However, the lack of intellectual property (IP) designs for easy implementation and integration of SOI with standard complementary metal-oxide- semiconductor (CMOS) processes in the industry and the high cost of SOI are deterring chip manufacturers from adopting it. Despite this, emerging applications such as capacitor-less memory, electronics for by-wire technology, bipolar CMOS (BiCMOS), radio frequency identification (RFID) and micro-electro-mechanical-system (MEMS) expect to increase demand for SOI wafers in near future.

Frost & Sullivan's (http://www.ti.frost.com ) new study, Emerging Trends in SOI Technology, provides analyses of CMOS-SOI, novel SOI devices, SOI-MEMS, capacitor-less memory, micro-opto-electro-mechanical-system (MOEMS), III-V compound materials-on-insulator and others.

If you are interested in a virtual brochure, which provides manufacturers, end users, and other industry participants with an overview of the Emerging Trends in SOI Technology, then send an e-mail to Tori Foster, Corporate Communications, at tori.foster@frost.com with your full name, company name, title, telephone number, fax number, e-mail address, city, state, and country. We will send you the information via e-mail upon receipt of the above information.

"The semiconductor industry is constantly struggling to meet demands for faster speed and lower power consumption, and SOI technology is playing an important role in achieving the scaling objective," says Frost & Sullivan Research Analyst Dr. Jayson Koh. "SOI designs can reduce parasitic capacitance tremendously and boost the current drive by reducing losses through leakages. It also allows devices to be packed closer through good device insulation."

Reduced junction capacitances and body effect result in SOI speed improvement. This improvement is equivalent to a speed difference between two back-to-back technology nodes. Thus, SOI technology enables products built on SOI wafers to be one generation ahead of the same products on bulk CMOS process. In addition, SOI is better suited for low-power and low-voltage applications than bulk silicon because of low parasitic junction capacitance and superior transistor on-off characteristics.

However, the high costs of SOI wafers have kept cost-sensitive applications at bay. Typical cost increase for switching to SOI wafers is in the range of 10 to 20 percent. On the other hand, supply for wafers has always been a problem. The current global SOI wafer supply is too low and monopolized by a few small manufacturers.

"Chip manufacturers are concerned with the reliability of the supply and cost of SOI wafers, as significant risks are involved if the supply is not steady," notes Koh. "This would be especially detrimental during high-volume production, as production schedules in the semiconductor industry are extremely tight."

However, the situation is improving. Supply is likely to increase with the licensing of more SOI manufacturing technology and new fabs slated for production. Moreover, cost has fallen over the years due to growing competition and volume. Increasing number of lithography and processing steps have also significantly raised manufacturing costs of wafers, which reduces the negative impact of high SOI wafer price.

Emerging Trends in SOI Technology is part of the Semiconductors Subscription, and it includes key drivers, challenges, restraints, analysis, and forecasts of technologies that may shape the future of the semiconductor testing industry. In this study, Frost & Sullivan's expert analysts thoroughly examine the following markets: semiconductor device and semiconductor manufacturing. Interviews are available to the press.

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