ARC processor core optimized for Xilinx FPGAs
ARC processor core optimized for Xilinx FPGAs
By Michael Santarini, EE Times
July 3, 2000 (11:13 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000703S0026
SAN MATEO, Calif. Xilinx Inc. and ARC Cores Ltd. have announced the availability of ARC's 32-bit configurable processor targeted for the Xilinx Vertex and Spartan-II FPGAs. The move appears to be a tit-for-tat response to Altera Corp.'s announcement that its Excalibur family of field programmable gate arrays will embed MIPS and ARM microprocessors. Xilinx and ARC have optimized the ARC 32-bit configurable core for the Vertex or Spartan-II FPGAs, in a traditional approach that differs from the one Altera employs with Excalibur, which can embed in silicon an ARM, MIPS or Altera internally-developed processor with a large block of programmable logic, Mark Bowlby, manager of the AllianceCore program at Xilinx (San Jose, Calif.), said flexibility is the key to the announcement with ARC. He said Xilinx chose the more traditional soft -core approach because it allows for greater design flexibility and can be targeted for a wider range of applications. Jim Turley, vice president of marketing at ARC Cores (Elstree, England), said matching ARC's configurable core with Xilinx's configurable logic devices is a "perfect fit." ARC's approach "allows the customer to reconfigure a processor to do exactly what's needed. So rather than getting a CPU designed 10 years ago, you are now given a configurable processor and can customize it to do exactly what you want. You need configurable logic to do that." Turley said that several ARC customers had previously used Xilinx devices for prototyping, but now, thanks to larger gate-count FPGAs, users can now employ the core on FPGA end-applications. "The combination gives you an amazing amount of freedom to explore your design alternatives," said Turley. "In an hour or two, you can try a completely different microprocessor approach. You can change buse s and instructions and empirically try out different alternatives to see the benefit of it. There is no way you can do that without configurable logic and a configurable processor." Traditionally, however, programmable logic hasn't been able to muster up the performance of standard-cell implementations. Bowlby said that customers have been able to get 150-MHz performance out of new Vertex devices using four levels of logic, and that new versions with up to 200-MHz performance are coming shortly. "In FPGAs, performance depends on the way designs are implemented," said Bowlby. "But the ARC can run at a slower speed and still do the amount of work required, so there is less need to drive performance." To help customers get maximum performance with the ARC and Xilinx combination or to help customers move into new application areas, the two companies have geared up their respective services programs. ARC has arranged a network of ARC Certified Design Centers (ACDCs) that can help customers implement ARC cores in Xilinx devices. Netlist helpers The companies are also qualifying new ACDC firms to deliver optimized Xilinx netlist implementations of preconfigured ARC processors. The charter members of this program are White Eagle Systems Technology (San Jose, Calif.), Fraunhofer Institute IIS (Erlangen, Germany), and Delta (Horsholm, Denmark). Turley said ARC Cores has also developed a new version of its ARCangel hardware prototyping development system that includes a Vertex XCV1000-6 FPGA. The ARCangel II allows ACDC members and fully licensed users to configure, test and iterate their ARC-based designs in either a Vertex or Spartan-II FPGA before committing their systems to board-level design. The reconfigurable nature of both the ARC processor and the FPGA delivers flexibility for optimization that is unavailable for hard-wired, processor-based solutions. The companies said the agreement is not exclusive, leaving ARC, for example, free to team with another programmab le logic company. Customers can purchase a full license for the ARC core, including the core configuration utilities, development tools and the ARCangel board directly from ARC Cores. Users can also purchase optimized Xilinx netlists for application-specific configurations of the ARC cores from ACDC member companies who can also integrate those into complete chip and board-level designs. Information on the ARC products is available at the Xilinx IP Center (www.xilinx.com/ipcenter).
Related News
- Bluespec, Inc. Releases Ultra-Low Footprint RISC-V Processor Family for Xilinx FPGAs, Offers Free Quick-Start Evaluation.
- Bluespec, Inc. Joins the Xilinx Partner Program, Offering Drop-in Ready RISC-V Processors for Xilinx FPGAs
- Arm expands design possibilities with free Cortex-M processors for Xilinx FPGAs
- Synopsys Introduces Optimized DTS-HD Decoder for DesignWare ARC Audio Processors
- Xilinx Expands Market-Leading Automotive Silicon Portfolio With Spartan-6 FPGAs Optimized to Reduce System Cost
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |