Commentary: Why it's time to redefine ESL
By Steve Glaser, Cadence Design Systems
Nov 3 2006 (13:48 PM), Courtesy of EE Times
Electronic system level (ESL) has frequently been characterized as the new frontier in the EDA industry as we move to higher levels of abstraction and advanced automation. However, there have been few companies able to deliver solutions that offer the ease of adoption, robustness, and measurable value necessary to support a sustained, profitable business. This is mostly because the ESL "definition" itself has remained ambiguous, causing many to wonder — what really is ESL and will it ever deliver on its promises?
Most of what is thought of as traditional ESL is design-centric. Current solutions are targeted to C-based systems designers, and are isolated from those driving the functional verification process, enforcing the system specifications across the entire project at block, chip and system levels.
As a result, today's narrow and isolated ESL "solutions" end up missing the mark, resulting in more questions than answers. So we are left with a user community unable to embrace the vast potential and visibility of ESL within the EDA industry.
What if system-level design solutions were not isolated from the rest of the design and verification activities? Should the ESL market definition include newer system-level verification solutions? Should software integration and verification be part of ESL, even if it doesn't use C-level models?
Should systems integration and verification towards the end of the design process be considered a necessary part of an ESL solution? Is hardware emulation considered part of ESL, since 80 percent of its users are verifying software and systems with it? Is system-level really about system-level abstractions or system-wide scope? Maybe the ESL definition should be revisited.
E-mail This Article | Printer-Friendly Page |
Related News
- Commentary: ANSI C won't work for ESL
- Commentary: Why we don't have IP quality yet (by Larry Cooke, VSI)
- Why have all broadcast powerhouses embraced intoPIX JPEG XS? Unraveling the secret behind industry leaders' unanimous adoption!
- Siemens' new Calibre DesignEnhancer boosts Samsung Foundry design quality and speeds time to market
- Microchip Slashes Time to Innovation with Industry's Most Power-Efficient Mid-Range FPGA Industrial Edge Stack, More Core Library IP and Conversion Tools
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards