eASIC rolls 90-nm structured ASIC line
(11/08/2006 9:54 PM EST)
SANTA CLARA, Calif. — FPGA vendors claim that they have conquered the ASIC for high-end designs. Some, however, believe that the battle is far from over. Seeking to displace FPGAs and other chip technologies in the marketplace, eASIC Corp. on Wednesday (Nov. 8) came out of its shell with a bang by unveiling a new 90-nm structured ASIC line. The company also disclosed a new foundry partnership with Fujitsu Ltd. and an EDA arrangement with Magma Design Automation Inc.
eASIC's 90-nm offering, dubbed Nextreme, is a family of six programmable structured ASICs, ranging in densities from 350,000 to 5 million gates — at performance levels up to 350-MHz. The Nextreme parts are quick turnaround devices that provide higher speeds but lower power levels than competitive FPGAs and ASICs, according to Ronnie Vasishta, chief executive for eASIC (Santa Clara, Calif.).
The fabless ASIC house also disclosed that it will no longer use STMicroelectronics Inc. (Geneva) as its main foundry. With its older-generation, 130-nm structured ASIC lines, eASIC had its parts built by STMicroelectronics on a foundry basis using a direct-write electron-beam manufacturing process.
E-mail This Article | Printer-Friendly Page |
|
Related News
- Fujitsu hurries 90-nm structured ASIC
- UMC rolls out 90-nm process, says pilot production due in 1Q 2003
- Synopsys Achieves Two IP Firsts: 65-nm PCIe and 90-nm USB Compliance Utilizing Common Platform Technologies
- Mosis offers IBM 90-nm process on MPW
- TSMC: Consumer market, 90-nm driving foundry sales
Breaking News
- Jury is out in the Arm vs Qualcomm trial
- Ceva Seeks To Exploit Synergies in Portfolio with Nano NPU
- Synopsys Responds to U.K. Competition and Markets Authority's Phase 1 Announcement Regarding Ansys Acquisition
- Alphawave Semi Scales UCIe™ to 64 Gbps Enabling >20 Tbps/mm Bandwidth Density for Die-to-Die Chiplet Connectivity
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models