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Faraday Pioneers in Providing On-Chip Variation (OCV) Information for Cell Libraries
Hsinchu, Taiwan and Sunnyvale, California -- November 16, 2006 -- Faraday Technology (TAIEX: 3035), a leading fabless IP and ASIC provider, today announced the availability of a new release of its 0.13 µm library with an advanced Location, Level, and Cell-Based On-Chip Variation (LLC-OCV) analysis methodology. Precise statistics of this LLC-OCV library and methodology can greatly enhance the accuracy and efficiency of Static Timing Analysis (STA) and this feature is especially important for the very deep sub-micron designs with large chip sizes and multiple gate levels. Faraday's silicon proven 0.13 µm LLC-OCV library and the upcoming 90 nm series are both applicable to all the prominent industry standard EDA tools.
Faraday's advanced built-in OCV library provides location, level, and cell-based OCV analysis to address the effects of on-chip statistical process variation, which can no longer be ignored in 0.13 µm designs or below. Most significantly, it improves timing accuracy and reduces the effort for timing closure, thus increasing the productivity for 0.13 µm timing signoff. The OCV methodology can save the chip size while speeding up time to market and assuring of high product yield, and it is so very easy to implement!
"With our new advanced OCV library and methodology, Faraday has established itself as the innovator and leader in 0.13 µm static timing analysis and signoff," said Dr. George Hwang, Vice President of R&D and International Business, Faraday. "Its introduction makes us the first ASIC/SIP vendor who offers the back-end intra-die timing analysis total solution for 0.13 µm ASIC designs."
About Faraday's LLC-OCV Library and Methodology
The traditional OCV methodology uses a constant derating factor and may impose unnecessary performance penalties on 0.13 µm designs, including reduced performance, larger die sizes and longer design cycles. Faraday's advanced OCV library and methodology use variable derating factors based on the gate level, physical location, and the respective used cell to select the optimal derating factor for each timing path. This enhances the accuracy of timing analysis, eliminates unnecessary timing violations, and allows design teams to rapidly achieve timing closure.
The 0.13 µm HS library with the OCV technology is currently available. The 90 nm series will be ready by Q1 2007.
Faraday's advanced built-in OCV library provides location, level, and cell-based OCV analysis to address the effects of on-chip statistical process variation, which can no longer be ignored in 0.13 µm designs or below. Most significantly, it improves timing accuracy and reduces the effort for timing closure, thus increasing the productivity for 0.13 µm timing signoff. The OCV methodology can save the chip size while speeding up time to market and assuring of high product yield, and it is so very easy to implement!
"With our new advanced OCV library and methodology, Faraday has established itself as the innovator and leader in 0.13 µm static timing analysis and signoff," said Dr. George Hwang, Vice President of R&D and International Business, Faraday. "Its introduction makes us the first ASIC/SIP vendor who offers the back-end intra-die timing analysis total solution for 0.13 µm ASIC designs."
About Faraday's LLC-OCV Library and Methodology
The traditional OCV methodology uses a constant derating factor and may impose unnecessary performance penalties on 0.13 µm designs, including reduced performance, larger die sizes and longer design cycles. Faraday's advanced OCV library and methodology use variable derating factors based on the gate level, physical location, and the respective used cell to select the optimal derating factor for each timing path. This enhances the accuracy of timing analysis, eliminates unnecessary timing violations, and allows design teams to rapidly achieve timing closure.
The 0.13 µm HS library with the OCV technology is currently available. The 90 nm series will be ready by Q1 2007.
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