English
Commentary: Lower test costs start with IC design
James T. Healy, CEO of LogicVision, Inc.
(11/23/2006 9:00 AM EST), EE Times
What do cost of test and weather have in common? To paraphrase Mark Twain, it seems like everybody talks about it, but nobody does anything about it. We can't do much about the weather but we can do something about test costs.
A few semiconductor industry leaders have figured out how to contain this problem by attacking test costs at the source — at the chip design level. But this perspective on cost reduction requires such a great degree of both creative thinking and corporate resolve that many businesses may find it challenging to create the necessary motivational changes to reap the reward.
Everybody agrees that cost of test is rising. At the recent International Test Conference (ITC) in Santa Clara California, Nvidia Corp.'s Chris Malachowsky said that test accounts for about 4-5 percent of the manufacturing cost. In addition, he said, yield costs, which include the costs for final testing and packaging, add an additional 5.5 percent to the total cost.
(11/23/2006 9:00 AM EST), EE Times
What do cost of test and weather have in common? To paraphrase Mark Twain, it seems like everybody talks about it, but nobody does anything about it. We can't do much about the weather but we can do something about test costs.
A few semiconductor industry leaders have figured out how to contain this problem by attacking test costs at the source — at the chip design level. But this perspective on cost reduction requires such a great degree of both creative thinking and corporate resolve that many businesses may find it challenging to create the necessary motivational changes to reap the reward.
Everybody agrees that cost of test is rising. At the recent International Test Conference (ITC) in Santa Clara California, Nvidia Corp.'s Chris Malachowsky said that test accounts for about 4-5 percent of the manufacturing cost. In addition, he said, yield costs, which include the costs for final testing and packaging, add an additional 5.5 percent to the total cost.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Virage Logic Delivers Faster Time-to-Market, Lower Test Costs, Smaller Area and Better Yield with Third-Generation STAR Memory System(TM)
- Commentary: More chip makers going 'fabless' to lower costs
- LogicVision announces new generation embedded test solutions -- LV4 enbling rapid delivery of quality SoCs at lower costs
- LogicVision calls on 'ET' 4.0 to lower test costs for SoCs
- Sondrel's latest reference IP platform enables ultra-powerful signal and data processing SoCs to be created faster for lower costs
Breaking News
- Baya Systems Raises $36M+ to Propel AI and Chiplet Innovation
- Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
- VeriSilicon and Innobase collaboratively launched second-generation Yunbao series 5G RedCap/4G LTE dual-mode modem IP
- ARM boost in $100bn Stargate data centre project
- MediaTek Adopts AI-Driven Cadence Virtuoso Studio and Spectre Simulation on NVIDIA Accelerated Computing Platform for 2nm Designs
Most Popular
- Alphawave Semi to Lead Chiplet Innovation, Showcase Advanced Technologies at Chiplet Summit
- Arm Chiplet System Architecture Makes New Strides in Accelerating the Evolution of Silicon
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Cadence to Acquire Secure-IC, a Leader in Embedded Security IP
- Blue Cheetah Tapes Out Its High-Performance Chiplet Interconnect IP on Samsung Foundry SF4X