Provis builds Verilog simulator with off-the-shelf parts

Provis builds Verilog simulator with off-the-shelf parts
By Richard Goering, EE Times
June 20, 2000 (3:32 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000620S0076

MINNEAPOLIS — A new hardware-based Verilog simulator, Z01X! from Provis Corp., is comprised entirely of off-the-shelf parts. Developed under a Department of Defense contract, the offering also provides concurrent fault simulation.

Z01X! runs on clusters of up to eight 64-bit Sun Ultra 60 workstations linked with a high-speed backplane. Users can either buy all of the required hardware from Sun and configure it to Provis' specifications, or purchase a rack-mounted system set up for Z01X! from Rave Computer Associates, a Sun authorized reseller. Rave's setup includes eight Ultra 60s, two Scalable Coherent Interface (SCI) 1.6-Gbyte/second switches, eight SCI interface boards, and cabling, all for less than $100,000. The Ultra 60s are general-purpose workstations that can be used for any other application.

Z01X! is an event-driven, compiled-code Verilog simulator that runs at the switch, gate, register-transfer and behavioral levels. "We map v ery high-speed primitives into hardware, just like an accelerator," said Tom Williams, president of Provis, which was spun off from Zycad, a now-defunct provider of gate-level accelerators, in 1994. As a result, Williams said, gate-level simulation speeds are four times that of a Zycad Paradigm XP accelerator.

Provis has not run benchmarks against contemporary Verilog software simulators. For behavioral and RTL code, which is not mapped into accelerated primitives, performance should be comparable to other compiled-code simulators, Williams said.

One key to the speed, said Williams, is the point-to-point communications enabled by the SCI boards, which he said allow much faster data transfers than Ethernet-based clusters. Eight CPUs, he said, provide about a fourfold speedup.

Z01X! software automatically partitions simulation runs and balances loads. Each process runs semi-autonomously and communicates over the SCI backplane. A "modular compile" function ensur es that when changes to a block are made, only the changed block needs to be recompiled. A link-on-the-fly technology loads the appropriate simulation blocks into the Sun hosts.

Each compiled block can be used as a standalone simulation, or as a functional block in a larger simulation. Different CPUs can simulate different chunks of the design, such as intellectual property blocks in a system-on-chip.

Not IEEE compliant

It should be noted, however, that Z01X! is not fully IEEE compliant because it doesn't support the Verilog programming language interface (PLI). "We are not great believers in the PLI," said Williams. "You have to know a lot about programming. We created a C-language behavioral interface that looks just like Verilog." This interface is called VC.

Z01X! does, however, produce standard Verilog charge dump (VCD) files. Provis states that any debugging tool that supports VCD should work with Z01X!, although so far the company has only tested it with Innoveda Inc.'s VirS im product.

Z01X! is also, according to Williams, "the only compiled-code, concurrent fault simulator in the world." It can run fault simulation across a cluster of Sun workstations, and then distribute the fault simulation across multiple clusters. Z01X! accepts behavioral fault models.

Z01X! is slated for a third-quarter production release, with prices starting at $25,000 for logic only and $50,000 for logic plus fault simulation.