Sarance Technologies Delivers Interlaken Protocol IP Core for Xilinx Virtex-5 FPGAs
New IP Core Implements Next Generation High-Speed Serial Chip-To-Chip Packet Interface
Ottawa, Ontario -- December 18, 2006 -- Sarance Technologies, a leading networking IP vendor, today announced the immediate availability of a Interlaken intellectual property core for Xilinx Virtex™-5 FPGAs. Interlaken is the next generation high-speed serial chip-to-chip protocol for transferring packets in networking systems. The availability of the IP core provides networking system manufacturers a low risk path for developing their next generation equipment.
“We have implemented a very efficient and flexible Interlaken IP core targeted for the high performance Xilinx 65nm Virtex™-5 Platform” said Farhad Shafai, Vice President, R&D at Sarance Technologies. “Our standard offering goes up to 40Gbps of payload bandwidth today, but the IP’s architecture is scalable, much like Interlaken, and allows us to build higher bandwidth cores as system performance increases.”
“Interlaken is steadily gaining traction within our Tier One customer base, demonstrating its potential to become the de-facto packet-based interface,” said Amit Dhir, director of Infrastructure Vertical Markets at Xilinx. “By leveraging our 65nm Virtex™-5 FPGA high-performance architecture and low power SERDES, customers have a highly-scalable solution, enabling optimized connectivity in a wide range of Internet Protocol-based Infrastructure Equipment designs.”
Price and Availability
Interlaken cores for the Xilinx Virtex™-5 FPGAs are available from Sarance Technologies now for 10-Gbps, 24-Gbps and 40-Gbps data rates. For information on other configurations and pricing, please contact Sarance Technologies at interlaken@sarance.com.
About Sarance Technologies
Sarance Technologies is an intellectual property development firm based in Ottawa, Ontario, Canada. Sarance offers a portfolio of ASIC and FPGA silicon IP cores targeted at vendors developing data communication solutions. Sarance specializes in developing classification engines, high speed interconnect, and other building blocks used in typical networking line cards. Sarance also offers consulting services for integrating its IP into FPGA or ASIC designs.
More information is available at www.sarance.com
|
Related News
- Xilinx Delivers Complete Virtex-5 FPGA Solution for XAUI Protocol
- Xilinx Delivers ISE WebPACK 9.2i - Offering Expanded Support for Latest 65nm Virtex-5 FPGAs
- Xilinx Delivers PlanAhead 9.1 Design Suite - Extends Performance Advantage of 65nm Virtex-5 FPGAs
- Xilinx Delivers Virtex-5 LXT FPGAs With Industry's First Built-In PCI Express Block And Low-Power Serial I/O
- Xilinx Delivers Virtex-5 LX Devices - World's First 65nm FPGAs In Customer Hands
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |