English
7 µW always on Audio feature extraction with filter banks on TSMC 22nm uLL
Commentary: Models hold value, not IP
Mitch Dale, Calypto Design Systems Inc.
(01/26/2007 2:54 PM EST), EE Times
While the intrinsic value of intellectual property (IP) is rooted in its functionality, it is the model that holds all practical value. Likewise, it is the model that generates most of the expense. The cost to develop, verify, maintain and support IP models is equal to that of designing an application specific integrated circuit (ASIC).
The trouble with models is that they come in all shapes and sizes, and there is no one shape that fits all needs. For a given IP core, there may be a high-level reference model, a cycle or transaction accurate system-level model used for software development and system architectural analysis.
Chances are, there's a register transfer level (RTL) model for implementation and multiple gate-level netlists optimized for various technologies. Depending on customer requirements, the provider may also supply models in multiple design languages and with interfaces. Very quickly, the effort of revision control and quality assurance dwarfs the cost of IP innovation.
(01/26/2007 2:54 PM EST), EE Times
While the intrinsic value of intellectual property (IP) is rooted in its functionality, it is the model that holds all practical value. Likewise, it is the model that generates most of the expense. The cost to develop, verify, maintain and support IP models is equal to that of designing an application specific integrated circuit (ASIC).
The trouble with models is that they come in all shapes and sizes, and there is no one shape that fits all needs. For a given IP core, there may be a high-level reference model, a cycle or transaction accurate system-level model used for software development and system architectural analysis.
Chances are, there's a register transfer level (RTL) model for implementation and multiple gate-level netlists optimized for various technologies. Depending on customer requirements, the provider may also supply models in multiple design languages and with interfaces. Very quickly, the effort of revision control and quality assurance dwarfs the cost of IP innovation.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Commentary / Analysis: Real men have fabs, but maybe not Infineon, NXP, TI and ST.
- PhySim system debugs hardware, not models
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- TSMC Will Not Take Over Intel Operations, Observers Say
- RaiderChip Hardware NPU adds Falcon-3 LLM to its supported AI models
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset