TransEDA tool aims to catch bugs earlier, improve design reuse

TransEDA tool aims to catch bugs earlier, improve design reuse
By Peter Clarke, EE Times
June 6, 2000 (9:26 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000606S0080

LONDON—TransEDA Inc. (Los Gatos, Calif.) has introduced a new type of tool into its Verification Navigator range of EDA tools-a parameterized-design rule checker called VN-Check that operates on VHDL or Verilog design files.

At this week's Design Automation Conference, the company announced it had doubled the performance of its established VN-Cover code coverage tool and increased the capacity of VN-Optimize, its test suite optimization engine, by a factor of 100. Those claims accompany the most recent release of Verification Navigator, version 6.1.

The company claims its new VN-Check tool goes beyond "dumb" syntax checking or static "linting" tools and allows designers to check for consistency and compliance with particular design styles that are expressed in an extensive rules database. These styles can be based on clocking or reset schemes, naming conventions, the number of entities allowed in case statements and many other features, and can be amended by corporate CAD groups.

The new tools identify design bugs earlier, before they break downstream tools, and it improves the reuse of existing designs, according to TransEDA. And because VN-Check has dynamic rule checking, rule sets can be applied on a project, group or companywide basis.

"VN-Check catches bugs before anything else can even see them. It's the ultimate in flexibility for both individual designers and corporate CAD groups. Simple linting tools with a static rule set just don't offer the flexibility and control needed for regular use," Borgstrom said.

Portable code touted
To promote design reuse of third-party modules, VN-Check not only ensures that the HDL code is portable between different languages and tools, but it also renders the code more readable and better documented for future reuse.

More than 400 built-in design rules for both Verilog and VHDL ship with VN-Check, and they include specific checks for synthesis and simulation. Actions taken w hen rule violations are detected can be customized for each rule with three levels of severity—note, warning or error—and customized messages.

For design teams and CAD groups that need more flexibility in defining rules, VN-Check offers an API and a custom rule generator (CRG) to implement complex new rules. Rules are specified using Java.

The CRG creates the necessary interface code and compiles the user-defined rule into a format that VN-Check can read. "Tcl was considered but was not found to be sufficient for some of the checks we wanted to do," Borgstrom said.

VN-Check for Verilog is already available in a standalone configuration. It will be fully integrated into Verification Navigator in July with support for Verilog and VHDL. Verification Navigator tools run under the Unix and Windows NT operating systems.

List price starts at $15,000 for a single language when bundled with the base configuration of Verification Navigator and $20,000 as a standalone product. The rule chec ker API and CRG sell for $45,000 per floating license. More information is available from TransEDA.