Mentor Graphics First to Provide Co-Verification Support for MIPS32 34K Multi-Threading Processor Cores
WILSONVILLE, Ore., March 12, 2007 – Mentor Graphics® Corporation (Nasdaq: MENT) today announced a new processor support package (PSP) for the MIPS32® 34K™ family of processor cores. Developed jointly with MIPS Technologies, this new C-based PSP supports transaction-level (TLM) and register-transfer level (RTL) simulation to give engineers a consistent platform upon which to view, validate and co-verify the multi-threaded hardware/software interactions occurring on the 34K processors.
Processing multiple software threads in parallel, the MIPS32 34K cores deliver significant gains in system performance and cost savings, with a very modest increase in die size. However, taking full advantage of these capabilities requires a powerful verification approach that allows designers to see parallel operations simultaneously.
“In multi-threaded processing, the hardware/software interactions of the system become intensely complex. Mentor Graphics’ processor support package gives our customers insight into high-level activity across multiple threads, as well as detailed activity on any single thread,” said Jack Browne, vice president of marketing at MIPS. “The result is a design flow that makes it easier for our customers to maximize the performance potential of applications based on our 34K processor family.”
The cycle-accurate PSP for MIPS32 34K processors is designed to work with the Mentor Graphics Seamless® co-verification tool, the first co-verification tool to support the 34K core family. The Mentor Graphics solution supports detailed views of the design, down to registers, system busses, and memory activity. The new Seamless PSP also supports comprehensive views of a 34K core’s virtual processing elements (VPEs) and thread contexts (TCs) to simplify verification and debug of software execution in a multi-threading system which can even include multiple operating systems running on a single 34K core. These capabilities enable engineers to optimize system performance and resolve hardware/software integration problems early in the design cycle, avoiding late-stage silicon re-spins that can cost millions of dollars.
“Mentor Graphics teams with industry-leading CPU vendors like MIPS Technologies to help our mutual customers maximize the value of their processor investments,” said Serge Leef, general manager of the System-Level Engineering Division at Mentor Graphics. “With this Mentor/MIPS combination, hardware engineers get a consistent, efficient system validation and co-verification platform that they can leverage throughout their electronic system level (ESL) and traditional RTL design processes.”
Availability
The Seamless PSP for the MIPS32 34K family is currently available from Mentor Graphics. For technical and pricing information, please email seamless_info@mentor.com. To find additional product information and technical papers, register for free Seamless workshops and functional verification seminars, please visit www.mentor.com/products/fv/hwsw_coverification/.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,250 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
|
Related News
- Mentor Graphics Seamless Co-Verification Environment First to Support Infineon Technologies TriCore 32-Bit Unified Processor for Embedded Systems
- Mentor Graphics Enables Hardware/Software Co-Verification with StarCore Processor Models
- Mentor Graphics Offers Co-Verification Model Support for ARCtangent User-Customizable RISC/DSP Designs
- Mentor Graphics Extends Co-Verification Support for the Motorola PowerPC Architecture
- Mentor Graphics' Nucleus RTOS and EDGE Tool Suite Support MIPS32 34K Family of Processor
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |