SiliconBackplane unsnarls memory bottlenecks
![]() |
SiliconBackplane unsnarls memory bottlenecks
By EE Times
June 5, 2000 (2:44 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000605S0028
A new version of the SiliconBackplane MicroNetwork from Sonics Inc. (Mountain View, Calif.) ups performance and attacks the communication bottlenecks and timing problems that plague system-on-chip (SoC) devices with shared-memory subsystems. Customers use the FastForward development tools that come with this this SoC-block communication management system to arrange cores and logic for optimum performance on a silicon backplane. When the SoC is taped out, the backplane becomes essentially a piece of intellectual-property (IP) glue logic tying the chip's blocks together, so Sonics draws an IP royalty. Pete Heller, director of marketing, said Sonics has improved the shared-memory management of SiliconBackplane MicroNetwork in the version 2.1 upgrade, adding 128-bit-wide data paths and single-ported protocols. Now, operating frequencies top 250 MHz and effective SoC bandwidths exceed 4 Gbytes/second. Heller said the older version handled bandwi dth of up to 2 Gbytes/s. Heller said Sonics customers have reported SiliconBackplane bandwidth utilization in excess of 80 percent for shared-memory-based SoC devices using on-board SRAM. With the new version, Sonics expects designers to attain over 90 percent SDRAM link efficiency while serving data flows from four or more traffic-initiating IP cores. Heller said the company also plans to extend the system's performance to DRAM and has entered into a technology partnership with Denali Software Inc., noted for, among other things, its memory-modeling tools. Denali will create an on-chip DRAM controller with speedy links to the system that will be able to access off-chip DRAM with maximum performance, he said. Version 2.1 will be available in the third quarter running on Sun workstations. Pricing starts at $125,000 for an IP license. Royalties are determined by user needs, applications and intended production volumes. See (www.sonicsinc.com.< /I>) Edited by Michael Santarini
Related News
- Sonics Unveils Industry's First IP Solution to Solve Memory Bottlenecks and Increase Memory Bandwidth Utilization
- CHERI Protects Memory at the Hardware Level
- Flash Memory LDPC Decoder IP Core Available For Integration From Global IP Core
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- OPENEDGES Technology Achieves ISO 26262 ASIL-B Certification
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |