English
Commentary: EDA is dead, software lives
Paul McLellan, EE Times
(03/16/2007 1:36 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=198001571
EDA is dead. Yes, it's still needed: We're not going to go back to designing chips with rubilith again. But the reality is that fewer and fewer chips are being designed, and most of the differentiation of a system is moving into the software. Even Gary Smith, the longtime Gartner analyst for EDA, proclaimed at the 2006 DAC that "It's the software, stupid." And then Gartner laid off Gary's EDA group, another symptom.
Historically, semiconductor economics have been the single driver behind EDA, especially during the 1980s and 1990s. By avoiding moving to the next process node, a company faced getting trampled by competition with offerings at half the cost. This is no longer the case. The only reason to consider a 45nm design is because you need something that you can't get otherwise, primarily density of transistors since even speed and power are not clearly moving in the right direction with each process node.
(03/16/2007 1:36 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=198001571
EDA is dead. Yes, it's still needed: We're not going to go back to designing chips with rubilith again. But the reality is that fewer and fewer chips are being designed, and most of the differentiation of a system is moving into the software. Even Gary Smith, the longtime Gartner analyst for EDA, proclaimed at the 2006 DAC that "It's the software, stupid." And then Gartner laid off Gary's EDA group, another symptom.
Historically, semiconductor economics have been the single driver behind EDA, especially during the 1980s and 1990s. By avoiding moving to the next process node, a company faced getting trampled by competition with offerings at half the cost. This is no longer the case. The only reason to consider a 45nm design is because you need something that you can't get otherwise, primarily density of transistors since even speed and power are not clearly moving in the right direction with each process node.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related News
- Siemens collaborates with Samsung Foundry to expand 3D-IC enablement tools, optimize other EDA solutions for foundry's newest processes
- INTERCHIP achieves 3x faster verification for next-gen clocking oscillator with Siemens' advanced analog and mixed-signal EDA technology
- Igniting Innovation: Siemens EDA launches Cre8Ventures in support of the EU Chips Act
- Siemens acquires Insight EDA to expand Calibre integrated circuit reliability verification offering
- Siemens extends leadership in EDA design-for-test with the launch of Tessent RTL Pro
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards