Test automation profile rises in IC design

NEW YORK -- May 30, 2000 -- Developments on tap for next week's Design Automation Conference in Los Angeles reveal the rising importance of test automation in the chip design process. The new capabilities also show that software-based test companies are quick to put breakthroughs in computer technology to work in test.

Among the advances to be unveiled in Los Angeles, Fluence Technology Inc. will detail a test-automation initiative for fabless semiconductor and service houses; Genesys Testware Inc. will show a full-chip behavioral-test synthesis tool; and SynTest Technologies Inc. will roll out Linux platform support for its design-for-test (DFT) solutions.

Fluence Technology (Beaverton, Ore.) calls its Fabless 2000 initiative a way of bringing test information to engineering teams during the design process. Based on a new set of software tools, the first of which is TestBenchPlus, Fabless 2000 aims to keep designers from doubling as test engineers or hiring expensive outside consultants.

"We're bringing test knowledge to the design team," said Hau Lam, product marketing manager at Fluence.

With TestBenchPlus, teams can start the production test cycle earlier in product development, when it is easier to fix design errors and test incompatibilities. In practice, teams use the product to do a preliminary ATE compatibility analysis at the design simulation phase. Thus, test issues can be wrung out.

TestBenchPlus' simple graphical user interface can be activated at the end of each logic simulation or automatic test pattern generation (ATPG) run. With Verilog, for example, running TestBenchPlus can help determine whether the Verilog Dump Change file will map onto a cycle-based timing tester. It also recommends artifact checks and repairs.

At the end of an ATPG run, TestBenchPlus helps verify whether the fault coverage will hold when scan dat a is run at-speed on a tester, whether scan data will compile on the tester and whether scan vectors will fit into its scan memory.

Model support

Also, the product tells which tester model is appropriate for a particular device and whether a foundry or test provider uses it. TestBenchPlus, which sells for $8,500, is said to support more than 90 ATE models.

For its part, Genesys Testware (Fremont, Calif.) is billing its Gtshell product as the first full-chip behavioral-test synthesis tool. Gtshell performs full-chip built-in self-test (BIST) resource allocation, architecture generation, interface synthesis and register-transfer-level insertion using Genesys' TestCore intellectual-property library.

The object is to help plan, select, interface and insert TestCores into leading-edge system-on-chip (SoC) designs, which can hold hundreds of memories and several logic cores.

An IC designer interacts with Gtshell using scripts written in the industry-standard Tool Command Language (T cl). Because Gtshell is written in Tcl, Gtshell scripts can be executed within any tool containing a Tcl interpreter, such as the Synopsys Design Compiler.

Genesys said that Gtshell contains Tcl functions that automate the integration of TestCore with popular memory compilers, synthesis tools and simulators.

The tool has drawn positive reviews from two companies that have used it. "Designers who combine the proven reliability of our Silicon Ready memory compilers with the capabilities of Gtshell will enjoy the benefits of faster time-to-volume in leading-edge SoC designs," said Mahesh Tirupattur, vice president of strategic accounts at Virtual Silicon Technology.

"Our Process-Perfect memory compilers combined with Gtshell allow customers to embed advanced memory self-test circuits in their ICs with minimum effort," said Jeff Lewis, marketing manager at Artisan Components.

The tool automatically generates complete synthesis scripts for Synopsys Design Compiler and Cadence Envisio Ambit. Comple te simulation scripts can also be generated for most Verilog and VHDL simulators, including Verilog-XL and -NC, VCS, ModelSim, VSS and VHDL-NC. Gtshell licenses start at $20,000.

Faster with Linux

The Linux operating system speeds DFT tool performance dramatically, according to L.T. Wang, president and chief executive officer at SynTest Technologies (Sunnyvale, Calif.). "Tool performance is critical to many of our customers," said Wang. "Our Linux tools typically run two to five times faster than other operating systems, depending on the workstation processor type and clock speed. This is in addition to the already five- to 20-times speed advantage that they have over competing solutions."

All of SynTest's DFT, BIST and ATPG tools are available for Linux platforms at the same price as Unix solutions -- from $20,000 for TurboCheck-Gate, a gate-level and RTL design and testability analyzer, to $150,000 for TurboScan, a full-scan and partial-scan synthesis and ATPG program. A memory BIST suite, boundary-scan test suite and fast fault simulator are also offered.