ARC Building Advanced CPF-Enabled Flow to Lower Power Consumption of its Configurable Subsystems and Cores
Effort Enhances Inherent Low Power Advantages of ARC's Configurable Solutions And will Benefit SoC Design for Portable Multimedia Applications
DESIGN AUTOMATION AND TEST CONFERENCE (DATE), France, April 16, 2007 – A member of the Power Forward Initiative and a leader in low power system-on-chip (SoC) design, ARC International (LSE: ARK) today announced it is building a new design flow that will enable SoC designers to further lower the power consumption of its configurable subsystems and processors. The new reference methodology is one of the first to be created leveraging Si2's Common Power Format (CPF) standard, and it will implement several low power features of Virage Logic's Area, Speed and Power (ASAP) Memory™ instances and ASAP Logic™ standard cell libraries. The new flow is being integrated into the patented ARChitect™ configuration tool, and is expected to be available to ARC customers in the second half of 2007.
The Power Forward Initiative is a broad-based program that is enhancing the worldwide electronics industry's ability to create lower power chips using advanced design techniques. ARC International is part of the industry initiative along with more than 20 other companies. A full listing of PFI members can be found at www.powerforward.org.
ARC's configurable subsystems and cores already are some of the semiconductor industry's lowest power solutions. For example, a configurable ARC® 750D core requires approximately one half the power of an ARM 1136 or a MIPS32 24Kc core with similar configurations and speeds. This is a key reason why ARC's configurable solutions are being broadly adopted for SoC designs targeting power-sensitive applications, such as portable multimedia devices. The new CPF-enabled reference methodology will further enhance ARC's existing low power leadership.
"Enabling ARC's growing customer base to create low power SoCs is one of our top priorities," said Paul Holt, vice president of product development and services at ARC International. "Working with leaders such as Cadence Design Systems and the Power Forward Initiative to implement CPF is one example of how ARC is delivering on that promise, and extending its leadership in low power chip design."
"IP providers understand the need to deliver low power intent along with their IP to customers. Cadence has the only CPF-enabled flow allowing a comprehensive low power solution," said Jan Willis, senior vice president of industry alliances at Cadence Design Systems, Inc. "As a key member of the Power Forward Initiative, ARC's role and proactive adoption of CPF are greatly valued."
"As one of the semiconductor industry's trusted IP partners, Virage Logic has been providing SoC designers with silicon-proven low power IP for nearly a decade," said Alex Shubat, vice president of research and development and chief technology officer at Virage Logic Corporation. "We are pleased to be an integral part of this reference flow to help our mutual customers realize significant power savings for their designs."
About the Power Forward Initiative
The Power Forward Initiative is an industry initiative sponsored by Cadence with the goal of enabling the design and production of more power efficient electronic devices. The Advisory Group consists of representative companies across the design chain from microprocessors to IP to foundries and semiconductor companies, and includes four EDA companies including Cadence. CPF v1.0 was contributed by Cadence to the Si2 Low Power Coalition in December 2006 and now is available as an Si2 standard to the industry at large.
About ARC International plcARC International is the world leader in configurable subsystems and CPU/DSP processors that are used by semiconductor companies worldwide to create system-on-chip (SoC) designs that provide a strategic competitive advantage. ARC’s patented configurable products are smaller, consume less power, are less expensive to manufacture, and provide a higher degree of differentiation over what can be created using "fixed architecture" core alternatives.
ARC International maintains a worldwide presence with corporate and research and development offices in California and Elstree, UK. For more information visit www.ARC.com. ARC International is listed on the London Stock Exchange as ARC International plc (LSE: ARK).
|
Related News
- Tensilica Collaborates with Cadence to Create CPF-Enabled Flow for Tensilica’s Multimedia Subsystems
- Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries
- Azuro's PowerCentric Reduces Power Consumption For ARC Configurable Subsystems and Cores by More Than 20 Percent
- SMIC Adopts Cadence Digital Flow With Advanced Features for Improving Area, Power and Performance
- Synopsys and UMC Release 65-Nanometer Low Power Design Flow Enabled by the Unified Power Format
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |