Aptix Launches Site for Emulation Configuration Services

SAN JOSE, Calif.----May 29, 2000--Aptix Corporation today announced that it is now offering a new Web-based service to configure system-on-chip (SoC) designs via the Internet for its emulation customers.

The new offering is called eSOCverify.com. This new site will enable Aptix customers to deposit their complex, proprietary SoC designs in a secure Web environment. The site will house all the software necessary to map and verify the emulation implementation. The key to the service is that Aptix consulting engineers can access the site securely from anywhere in the world at any time and have all the tools necessary to perform this service, 24 hours a day, seven days a week.

Aptix has recently increased the ease with which designs up to 3 million ASIC gates can be mapped into a single Aptix prototyping system for SoC emulation (see companion announcement of availability of dual-density Virtex 2000E prototyping modules). This greatly increased capacity, combined with the new Expedition emulation software, makes it possible for Aptix to efficiently deliver to customers a reprogrammable system for SoC verification that is also pre-configured to represent their design and is ready for debugging.

``We believe that eSOCverify.com will enable us to greatly expand our services delivery to three or four times as many customers as is otherwise possible,'' said Leif Rosqvist, chief operating officer at Aptix. ``With access from anywhere in the world via this environment, our consulting engineering resources will be much more efficient, resulting in lower costs that we will pass on to our customers. Configuration services are just the first step for Aptix. We will continue to utilize the power of the Internet to expand our services offerings to our customers.''

About Aptix Corporation

Aptix Corporation's products are used to verify system and system-on-chip (SoC) designs prior to integrated circuit (IC) and board tape-out and fabrication. Aptix's products utilize the block-based verification methodology, which provides a mechanism to map and verify individual design blocks incrementally and in parallel with the design creation process. This methodology shortens the net prototype creation time of achieving real-world operation of the prototype to the few days required to map and verify the last RTL block designed. Debugging designs becomes simple because the mapping process is both under the user's interactive control and follows the natural hierarchy of the design. This also makes tracing design problems back to the source netlist an intuitive process.

The company is privately held and is headquartered at 2880 North First Street, San Jose, California 95134. Telephone 408/428-6200, Fax 408/944-0646. Visit Aptix on the Web at http://www.aptix.com.

System Explorer and Explorer are trademarks of Aptix Corporation. Virtex is a trademark of Xilinx Corporation.

Contact:
     Aptix Corporation
     Linda Lavin, 408/428-6226
     or
     KVO
     LeAnne Frank, 503/221-7403