CAMPBELL, Calif. -- May 9, 2007 -- Silicon Interfaces, a high-end design services and leading provider for IPs in Europe, North America and Asia-Pacific, under their IP Development Program - Silicon Cores: Core to the Intelligent Systems™, today announced the availability of RapidIO Physical Layer Interface Open Vera Verification IP. The VIP is the latest addition to the portfolio of Silicon Interfaces Verification IPs.
Silicon Interfaces’ RapidIO Physical Layer Interface OpenVera Verification IP is a fully documented, off the shelf component for the verification of the RapidIO Physical Layer Interface Controller. RapidIO is a Packet-switched Interconnect primarily intended for an Intra-system Interface for chip-to-chip and board-to-board communications at Gigabyte-per-second performance levels.
OpenVera Verification is a comprehensive test bench automation solution for module, block and full system verification. Open Vera is an intuitive, high-level, object-oriented programming language developed specifically to meet the unique requirements of Functional Verification. OpenVera enables generation of high coverage, constraint-driven random stimulus generation. With OpenVera, it is easy to quickly model the target environment at a high level of abstraction while automatically generating constrained random stimulus.
Constraint driven random stimulus in Open Vera enables the detection of a wide range of bugs including functional and corner cases. Along with it, Open Vera supports Multilanguage Verification namely all HDLs including VHDL, Verilog and SystemC.
Product Highlights: - Full Randomized Flow Control of the Packets.
- Input number of Packets from the Command Line.
- Single User entry driven root-level Seed.
- Randomized selection of various Packet generation tasks.
- Optional Inclusion of OpenVera Assertions Engine.
- Score Board for User / Link Interface.
- Score Board for Fabric Interface.
- Optional Randomized Injection of Control Symbols on the Fabric Interface.
- Full Automation in conjunction with constraint-driven randomization.
- Loop-Back mechanism for the Packets transmitted by the DUT to the Fabric.
- Preliminary DUT Health Check-up, to check its heart beat prior to transmission.
- Randomizing pulsing of TIME-OF-DAY Control Symbol from User / Link
- Interface.
- Randomized Byte Enable for Data on User / Link Interface.
- Supported with ‘DEFINES’ file for Top-level OpenVera Testbench, User / Link and Fabric end tasks.
- Randomized Inter-packet gap generation.
- This product comes along with highly comprehensive documentation.
For a complete listing of features and pricing of RapidIO Physical Layer Interface OpenVera VIP, visit the Silicon Cores web site at
www.siliconcores.com Availability The RapidIO Physical Layer Interface OpenVera VIP is available now.
About Silicon Interfaces Silicon Interfaces has experience in verification solutions and developing IPs for Fabric Channel Interconnect, Telecom and Networking domains, including Bluetooth Baseband, Gigabit Ethernet MAC, SONET Framer STS-1/3, 1394, USB2 Function Controller, USB On-The-Go, USB 2.0 OVA Checker AIP, Infiniband, 8530, 8051, 7990, UART, Rapid IO , 802.11 a/b/g MAC, PCI-Express, 10 Giga and SONET STS Framer –12. These IP have had considerable maturity based on certification, targets to various FPGA devices and ASIC libraries, silicon area optimization, silicon prototyping and testing. Also available are OVA VIPs and an extensive driver development program which enables the company to offer a packaged solution to the customer. For more information please visit
www.siliconcores.com
