Cadence Extends Verification Resources With New Plan-to-closure Methodology Qualified Program
Initial 22 Worldwide Partners Address Advanced Verification Planning and Management, Assertion-Based Verification, Reuse, and System-level Development
SAN JOSE, Calif. -- May 09, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced 22 newly certified Incisive® Plan-to-Closure Methodology Verification Alliance Partners. The Plan-to-Closure Methodology-certified partners extend verification resources and expertise for design teams facing verification-resource limitations. Partners are trained and qualified in "high-demand" areas such as SystemVerilog, transaction-level verification, assertion and coverage-driven verification, and system-level verification.
In order to be certified, new members are required to attend Plan-to-Closure Methodology-based training and encouraged to get focused training in one of the four areas including: planning and management, assertions and formal, universal verification reuse, or full-system-level verification. Once members attend the course, they are signed off by a technical sponsor and gain Plan-to-Closure-Methodology certification.
"YOGITECH has been delivering quality verification IP for some time and we trust the Plan-to-Closure Methodology to address IP-integration challenges by helping us deliver high-quality verification IP," said Silvano Motto, CEO, Yogitech. "As an initial Plan-to-Closure-qualified member we look forward to continued improvement in our development process as we develop universal verification components in SystemVerilog and e."
"There's now broad acceptance that one of the keys to addressing verification complexity is a well engineered and executed methodology," said Rob Hurley, CEO, Doulos. "High-capability training that addresses both methodology and language is vital to effective execution. Our commitment to this program will enable customers implementing Plan-to-Closure-based environments get best-fit training."
Members are also encouraged to spend scheduled time contributing and participating in the Plan-to-Closure-Methodology Web community by sharing examples and experiences around verification-IP development and protocol expertise. This Web- based knowledge system allows for partners and users to seek advice, share ideas, and gain access to additional methodology resources to help automate IP adoption and facilitate reuse within system-level project development.
"XtremeEDA's broad experience implementing verification-methodology programs for leading customers made us qualified Plan-to-Closure-Methodology partners," said Claude Cloutier, CEO, XtremeEDA. "We found the approach to be extremely thorough with the ability to add much higher levels of predictability and scalability to plan, measure and react accordingly at the project level."
"Many organizations realize that they are up against serious verification-resource limitations, and need proven step-by-step options for designers," said Steve Glaser, corporate vice president, Marketing, Verification Division at Cadence. "These newly certified partners will add to the Plan-to-Closure-Methodology community, and make adoption and deployment of best practices simpler and much more readily available for our worldwide customers."
For more information on the Plan-to-Closure Methodology-Qualified Verification Alliance program, please visit, http://www.cadence.com/partners/verificationalliance/ipcm_members.aspx.
About Cadence
Cadence® enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
|
Cadence Design Systems, Inc. Hot IP
Cadence Design Systems, Inc. Hot Verification IP
Related News
- Synopsys Extends Verification FastForward Program, Enabling Cadence Incisive and Mentor Graphics Questa Users to Adopt VCS Simulation with Fine-Grained Parallelism Technology
- Cadence Extends the Open Verification Methodology Beyond SystemVerilog to Include SystemC and e Language Support
- Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud
- Cadence Shortens Automotive Verification Closure with New Verification IP for UFS 3.0, CoaxPress, and HyperRAM
- Mentor extends functional safety assurance program to key design, verification and analog/mixed signal products
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |