License-free, FPGA-based Single Chip Controller for Low Cost SERCOS III I/Os available
Typical target applications of Easy-I/O are encoders, measuring sensors, valve clusters, 24V digital I/O and analog I/O.
Easy-I/O can be very easily integrated in hardware designs. A free version of the core is provided for the Xilinx Spartan-3 XC3S250E device in a TQ144 housing. It supports 16 digital inputs and 16 digital outputs.
To provide easy access for interested companies, SERCOS International will offer Easy-I/O as a freely downloadable IP core via www.sercos.de/easy-io, to be active by the end of May. Companies simply need to register online. There are no license fees and a membership in the SERCOS Organizations is not required.
Registered users receive the IP core, as well as a functional description, complete documentation of the interfaces and a reference design. Technical support is provided via an online forum and FAQ lists. Updates and bug fixes of the IP core will be provided on a regular basis.
Background information:
To minimize the costs for a slave interface, the functionality of a SERCOS III slave was reduced to a minimum. Thus, the Easy-I/O IP core supports only the SERCOS III real-time and service channels. Up to 64-byte master real-time data and 64-byte slave real-time data can be processed. Ethernet frames that are transmitted within the Non-Real-Time (NRT) channel of a SERCOS III network are directly forwarded to the next network node. The asynchronous service channel is realized inside the IP Core and allows read and write access to the available parameter according to the standardized SERCOS III I/O profile. Easy-I/O supports the remote addressing functionality of SERCOS III, by which a SERCOS address is assigned to a node on the basis of a physical address and a specific device identification. The core supports cycle times down to 31.25 µs as well as the unique redundancy feature of SERCOS III to provide highly available automation concepts.
Related News
- Altera and TES Offer Cost-Effective FPGA-Based Reconfigurable Graphics Controller
- Lattice Accelerates Development of Low Power FPGA-Based Custom Solutions with Lattice Design Group
- Microsemi and Tamba Collaborate on New PolarFire Devices to Deliver Industry-Leading Low Power FPGA-Based 10G Ethernet Solution
- Xilinx, Northwest Logic and Xylon Provide Low Cost FPGA-based MIPI Interfaces for Video Displays and Cameras
- Altera and TES Partner on FPGA-Based PCI Graphics Controller IP
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |