Verifying the vendor tools

Just within the past month, we've seen some interesting rollouts. There's startup Avery Design Automa tion ( www.avery-design.com), which claims to have the first testbench automation tool to support Verilog HDL extensions and Verilog-C/C++ distributed simulation. Real Intent, another startup, offers Verix, claimed to be the first "intent-driven" verification tool. It reads your Verilog HDL, deciphers your intent and runs a series of static checks ( www.realintent.com).

U.K. startup Tenison Technology claims to break new ground with a cycle-accurate, Verilog-to-C compiler (www.tenisontech.com). Co-Design Automation has just come out with SystemSim, the first simulator for Co-Design's Superlog language (www.co-design.com). It also claims to be the first multilingual simulator that doesn't depend on programming language interfaces.

And then there's 0-In Design Automation, which has just come out with 0-In Search, portrayed as t he industry's first "semiformal" tool. It mixes formal model checking with simulation to track down difficult corner cases (www.0-in.com).

0-In's experience is instructive, however. In June 1998, it introduced 0-In Check, which inserted checkers in Verilog code. You didn't hear much about 0-In Check afterward. That's because customers found the tool needed much more sophisticated checks to be truly useful and competitive. A greatly enhanced 0-In Check was reintroduced last March.

Not all the new technologies will go through such a two-year hiatus. But all will need shakedown cruises in the real world, and there will be a learning curve for vendors and users. You're not really buying an off-the-shelf product with these new tools-you're partnering.

Those partnerships, however, were needed for every EDA tool in existence. And the rewards for early adopters are great when technology proves useful.