Avery Design Systems Announces Support for PCI Express IO Virtualization and AMBA AXI

ANDOVER, MA. -- May 24, 2007 – Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced that the PCI-Xactor verification solution will support the recently released PCI Express IO Virtualization (IOV) and Address Translation Services (ATS) standards. Avery also announced improvements in core-level verification for embedded PCI Express (PCIe) cores utilizing AMBA 3 AXI bridging interfaces and advancements in bug detection based on innovative sequential consistency checking.

“Early adoption of the PCI Express standards developments and our commitment to support the growing embedded SOC market utilizing PCI Express is an absolute for us to meet the critical technical requirements and market windows of our IP vendor partners and end user customers,” said Chris Browy, vice president of Avery Design.

PCI-Xactor support for the PCI Express IO Virtualization (IOV) and Address Translation Services (ATS) standards based on Single Root IOV (SR-IOV) will be available in June 2007 and Multi-Root IOV (MR-IOV) support is planned for H2'07 release. The solution is comprised of enhanced Root Complex, Endpoint, and Switch BFMs, protocol assertions, and a compliance test suite.

AMBA AXI and PCI Express are emerging as a powerful combination for high-performance embedded SOC design. Avery now supports a complete closed-end core-level verification environment to provide developers and users of PCI Express to AMBA AXI bridging with the needed AXI BFM additions in the compliance test framework. After mapping the application layer transactions onto a set of AXI transactors suited to the custom bridge configuration, the user can perform comprehensive compliance verification utilizing either Avery's Root Complex or Endpoint test suites. Avery's solution also supports comprehensive protocol checking of PCI Express Gen1/Gen2 and the solution can be further outfitted with the AMBA 3 AXI Assertions which are available directly from ARM.

Also announced today are new built-in features to detect and isolate bugs faster using co-verification and dynamic sequential consistency checking of a DUT and shadow reference model. Under this new methodology, compliance and systems tests are executed in both models and an innovative dynamic monitor performs transaction and sequential consistency analysis over a set of pre-configured design match points representing the major architectural state information found in the PCI Express specification. Co-verification is also especially useful in random test stimulus result prediction. The new Design Match option comes with library of checkers covering PHY, DL, TL layers and configuration space and targets:

• Link Training and Status State Machine (LTSSM) transitions
Retry buffer entries and replay trigger
• VC flow credits counters
• Configuration and status registers

About PCI-Xactor for PCI Express

The PCI-Xactor for PCI Express Verification Solution is a complete verification solution consisting of Bus Function Model (BFM), SuperMonitor, PCI-SIG compliance checklist assertions, test suites, and verification frameworks for functional verification of PCI Express components. The PCI-Xactor allows design and verification engineers to quickly and extensively test the entire functionality of their PCI Express compliant devices. Verification frameworks form complete testbench environments for endpoint, root complex, and switch designs.

Key Features

• Verilog source code format for BFMs and test cases
Complete set of fully functional BFMs and testbenches for every PCI Express component: Endpoint, Root Complex, Switch
• Support for serial, 10-bit symbol, and PIPE interfaces.
• Robust BFM API automates sending TLPs/DLLPs and controlling automatic BFM device response behaviors and link and device state transitions
• Supports transaction-oriented request-completion and error injection sequences based on address and command type attributes
• Inject errors and noise at all layers
• Root Complex provides BIOS enumeration functions to validate OS and PCI2.3 compatibility
• Test suites include the PCI-SIG-based compliance tests in addition to Avery-based endpoint, root complex, and switch test suites that target high compliance coverage from their corresponding checklists
• Test are self-checking, portable, and reusable on most types of designs
• Sequential consistency checking using design matchpoints
• SuperMonitor verifies transaction ordering in N-port switch and bridge designs
• Native programming interfaces for Vera, SystemVerilog, SystemC, VHDL, C/C++

About Avery Design Systems

Avery Design Systems Inc. is a supplier of functional verification products and service that enables dramatic productivity improvements of the ASIC-based systems and SOC verification process. Additional information about Avery Design Systems is available at http://www.avery-design.com.