Lightspeed Logic collaborates with Cadence to deliver Reconfigurable Logic Reference Flow
CPF-Enabled Low-Power Reference Flow for Mask Reconfigurable Logic Enhances Design Flexibility and Manufacturability for SOC and ASSP Designs
San Jose, CA, June 1, 2007 - Lightspeed Logic, the leading provider of mask reconfigurable IP, today announced immediate availability of the 65-nanometer Common Power Format (CPF)-enabled reference flow for Lightspeed Logic’s Reconfigurable Logic IP. This reference flow enables SOC designers to accelerate time-to-market for low-power designs using Lightspeed Logic’s Reconfigurable Logic IP.
“We are pleased to collaborate with Cadence in the creation of this reference flow, delivering unparalleled quality of results to our mutual customers,” said Dave Holt, President and CEO, Lightspeed Logic. “Together with our Reconfigurable Logic, this flow allows customers to meet timing, signal-integrity, low-power requirements, and design-for-manufacturability objectives more rapidly, and with better quality of results than alternative solutions.”
SOC designers are now enabled to create a flexible chip architecture, significantly reducing design cost and speeding time-to-market. The lithography-aware routing in the reference flow coupled with the regular structure of the Reconfigurable Logic tile-based architecture helps reduce lithography related variability challenges at 65 nanometers and below. The reference flow is a complete flow from RTL to GDSII incorporating the CPF-based Cadence® Low Power Solution including design environments for logic synthesis, simulation, routing, functional verification, power optimization, timing and SI closure, and IR physical simulation coupled with Lightspeed Logic’s DesignBuilderTM tool, which is used for placement, mapping, clock tree synthesis, and buffering.
“We are pleased to work with Lightspeed Logic to add support of the Cadence Low Power Solution to their reference flow,” said Jan Willis, senior vice president of Industry Alliances at Cadence.“With the addition of Lightspeed Logic, ecosystem support for CPF continues to be the only proven solution and has the broadest list of industry support.”
Lightspeed Logic’s Reconfigurable Logic delivers a density and performance breakthrough for mask reconfigurable solutions, achieving 80 percent the density of traditional methodologies for multi-million gate logic blocks, twice the density of competing mask reconfigurable solutions.
Lightspeed Logic will introduce this flow at the Tech Talk titled "Reconfigurable Logic CPF Flow for Imaging, DTV and Basestation Applications" in the Cadence booth #2753 at the Design Automation Conference on Wednesday, June 6 from 10:30am to 11:00am, at the San Diego Convention Center.
About Lightspeed Logic
Lightspeed Logic is a provider of mask reconfigurable intellectual property (IP), a digital logic implementation technology that provides time-to-market, yield, manufacturability, and development expense advantages over standard-cell implementation. Founded in 1996, Lightspeed Logic has developed and brought to market four mask-reconfigurable architectures, the most recent of which is a regular logic structure available for multiple foundries, IDMs and process nodes. The company is currently working with customers at the 150, 90, 65, and 45 nm process nodes. Lightspeed Logic’s corporate headquarters are in Santa Clara, CA. You can find more information on Lightspeed Logic at www.lightspeed.com.
|
Related News
- Cadence Collaborates With Common Platform and Arm to Deliver 45-NM RTL-to-GDSII Reference Flow
- Cadence Collaborates with UMC to Deliver 65nm CPF-Based Low-Power Reference Design Flow
- UMC and Cadence Collaborate to Deliver 28nm Design Reference Flow for ARM Cortex-A7 MPCore-based SoC
- TSMC and Cadence Deliver 3D-IC Reference Flow for True 3D Stacking
- Synopsys and Virage Logic Collaborate on Test Reference Design Flow to Deliver Embedded Memory Test
Breaking News
- HPC customer engages Sondrel for high end chip design
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- TSMC drives A16, 3D process technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
E-mail This Article | Printer-Friendly Page |