English
TSMC Announces Active Accuracy Assurance Initiative
Drives design optimization and rapid time to market
Hsinchu, Taiwan - June 4, 2007 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced its Active Accuracy Assurance initiative, a comprehensive design-based program that will achieve new levels of accuracy for TSMC’s advanced process technologies. The initiative provides an on-going evolution of accuracy standards for all stages of the design and manufacturing value chain.
The new set of standards are developed through careful characterization, validation and co-optimization of critical sub-circuit building blocks that are closely coupled with TSMC’s process technology. TSMC design ecosystem partners who comply with these standards can provide assurance to designers that they can optimize their designs by reducing guard banding and avoiding overdesign. Designers working with EDA tools compliant with the initiative increase their prospects for first-time silicon success with lower costs and quicker time to market.
TSMC’s Active Accuracy Assurance initiative was started by data-mining TSMC’s own vast accumulation of manufacturing data. TSMC shares this data with EDA vendors and other ecosystem partners, who can then develop their own methodology in compliance with accuracy assurance standards. IP and library partners can use this data to enhance their IP performance, shorten their IP development cycle and deliver higher quality products to meet accuracy assurance standard. Design service partners, likewise, can derive from the same principle to ensure their service output comply with the standards that eventually delivers consistent quality benefit to the customers.
“TSMC’s Active Accuracy Assurance initiative provides higher standards of accuracy that are critical to achieve silicon success with 45nm and other advanced process technologies,” said Kuo Wu, deputy director of design service marketing at TSMC. “The initiative provides assurance to designers that they can maximize the performance of their designs without having to compensate or ‘guard band’ for unforeseen variations in the manufacturing process.”
TSMC’s Active Accuracy Assurance initiative is a broad program that encompasses all components of the design ecosystem. It provides standards of accuracy for all TSMC partners, including EDA vendors, IP providers and library developers, and Design Center Alliance (DCA) partners. TSMC applies the same standards to tools, building blocks, and technologies, including TSMC’s Reference Flow 8.0, design for manufacturability (DFM) tools, process design kits (PDK), design support, and backend services.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.
Hsinchu, Taiwan - June 4, 2007 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today announced its Active Accuracy Assurance initiative, a comprehensive design-based program that will achieve new levels of accuracy for TSMC’s advanced process technologies. The initiative provides an on-going evolution of accuracy standards for all stages of the design and manufacturing value chain.
The new set of standards are developed through careful characterization, validation and co-optimization of critical sub-circuit building blocks that are closely coupled with TSMC’s process technology. TSMC design ecosystem partners who comply with these standards can provide assurance to designers that they can optimize their designs by reducing guard banding and avoiding overdesign. Designers working with EDA tools compliant with the initiative increase their prospects for first-time silicon success with lower costs and quicker time to market.
TSMC’s Active Accuracy Assurance initiative was started by data-mining TSMC’s own vast accumulation of manufacturing data. TSMC shares this data with EDA vendors and other ecosystem partners, who can then develop their own methodology in compliance with accuracy assurance standards. IP and library partners can use this data to enhance their IP performance, shorten their IP development cycle and deliver higher quality products to meet accuracy assurance standard. Design service partners, likewise, can derive from the same principle to ensure their service output comply with the standards that eventually delivers consistent quality benefit to the customers.
“TSMC’s Active Accuracy Assurance initiative provides higher standards of accuracy that are critical to achieve silicon success with 45nm and other advanced process technologies,” said Kuo Wu, deputy director of design service marketing at TSMC. “The initiative provides assurance to designers that they can maximize the performance of their designs without having to compensate or ‘guard band’ for unforeseen variations in the manufacturing process.”
TSMC’s Active Accuracy Assurance initiative is a broad program that encompasses all components of the design ecosystem. It provides standards of accuracy for all TSMC partners, including EDA vendors, IP providers and library developers, and Design Center Alliance (DCA) partners. TSMC applies the same standards to tools, building blocks, and technologies, including TSMC’s Reference Flow 8.0, design for manufacturability (DFM) tools, process design kits (PDK), design support, and backend services.
About TSMC
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry industry’s largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company’s total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.
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