Taiwan's Etron, TSMC claim smallest low-power 8-Mbit SRAM with 0.15-micron process
![]() |
Taiwan's Etron, TSMC claim smallest low-power 8-Mbit SRAM with 0.15-micron process
By Semiconductor Business News
May 12, 2000 (8:50 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000512S0001
HSINCHU, Taiwan -- Etron Technology Inc. and chip foundry Taiwan Semiconductor Manufacturing Co. Ltd. here announced the world's smallest 8-megabit low-power SRAM -- a memory chip measuring less than 40 mm2. The 8-Mbit SRAM was developed by nine-year-old Etron, which claims to be Taiwan's largest fabless memory company. The chip is based on TSMC's 0.15-micron process technology. "TSMC is the first dedicated foundry to introduce a commercially available 0.15-micron process and to deliver wafers at that technology node," said Shang-Yi Chiang, vice president of R&D at TSMC. "Cooperating with Etron Technology, TSMC has manufactured the most competitive product on the market in the shortest period of time, demonstrating the powerful capabilities of our 0.15-micron process technology." According to Nicky Lu, chairman of Etron, the 8-Mbit low-power SRAM was fully functional "even in the first pilot lot and achieved high yield without re pair." He said Etron is confident the product will reach volume production in the third quarter of 2000 with high levels of yields. The memory operates at 1.5 and 1.8 volts, but matches the performance of other SRAMs running with 3-volt supplies, Lu said. "This chip is targeted for high-end cellular phones using the wireless application protocol (eWAP), this will enable system developers to march into more advanced eWAP generations," he added.
Related News
- TSMC implements MoSys' new low-power 1T-SRAM for 0.13-micron process
- eMemory Technology Inc. announces the launch of Neobit one-time programmable (OTP) IP on 0.15-micron high voltage process
- SMIC Enhances IP Portfolio with Artisan's 0.15-Micron IP Platform
- Virtual Silicon Introduces Industry's First Low-Power 0.13-Micron Product Line
- Pixim introduces low-power imaging architecture based on TSMC 0.18-micron CMOS
Breaking News
- JEDEC® and Industry Leaders Collaborate to Release JESD270-4 HBM4 Standard: Advancing Bandwidth, Efficiency, and Capacity for AI and HPC
- BrainChip Gives the Edge to Search and Rescue Operations
- ASML targeted in latest round of US tariffs
- Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion
- Creonic Unveils Bold Rebrand to Drive Innovation in Communication Technologies
Most Popular
- Cadence to Acquire Arm Artisan Foundation IP Business
- AMD Achieves First TSMC N2 Product Silicon Milestone
- Why Do Hyperscalers Design Their Own CPUs?
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- New TSN-MACsec IP core for secure data transmission in 5G/6G communication networks
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |