Faraday Launches Silicon-Proven DDR2 Memory Physical Interface IP

Complete solution to enable customers to speed the system integration and lower the design risk, without performance compromise

Hsinchu, Taiwan -- June 26, 2007 -- Faraday Technology (TAIEX: 3035), a leading ASIC and IP provider, today announced the availability of DDR2 physical interface (PHY) IP in UMC 0.13um and 90nm process. Faraday’s DDR2 PHY IP, a reliable, cost-effective, and easy-to-integrate memory interface solution, enables semiconductor companies, in a timely manner, to make high performance DDR2 memory interface System-on-Chips (SoCs) for their consumer, automotive, industrial and medical applications.

DDR2 interface is vital to develop innovative applications, and nowadays SoC designers especially demand high-speed and low-power DDR2 solution with the hope for balancing both the cost and performance. However, the benefit of adopting DDR2 interface is usually coupled with weighty implementation challenges, especially the impedance discontinuities together with signal and voltage integrity caused by impedance mismatch.  Designers need to spend a considerable amount of time managing not only on-chip IP blocks integration but also off-chip signaling details when delivering high-performance DDR2 interfaces. This situation will especially get aggravated if IP blocks are acquired from multiple vendors.

Faraday’s single-vendor DDR2 physical Interface IP, leveraging the company’s unique strength in analog I/O buffer circuit design, provides precision output driver impedance, and offers customers a superior way of tackling system level signal integrity issues. Designers using Faraday’s DDR2 IP can gain excellent signal quality for a full range of PCB route impedance, termination tolerance, and a variety of board topologies; thus, it can expand system timing budget and help resolve timing closure problems.

"We are glad to launch this production-ready DDR2 PHY IP to meet customers demand for a robust and failsafe memory interface solution.  The complete solution that includes SSTL18 I/Os, data synchronization module, and analog DLL will reduce the designers integration effort to a great extent," said Hsin Wang, vice president of IP Business and Technology at Faraday. " Furthermore, uniquely considering off-chip conditions in our design allows customers to attain the highest performance/ cost ratio during the board design phase, and ultimately enhances their overall competitiveness."

About Faraday’s DDR2 PHY:

• SSTL18 compliant with JEDEC JESD8-15
• Differential data strobe
• Support X8, X16 and X32 DRAM organization
• Compliant to either a Point to Point or DIMM configuration
• Support auto calibrating P/N output driver impedance using OCD methods.
• On-chip decoupling capacitors to reduce SSO bounces
• Support multiple sets of programmable on-die termination(ODT)

Many different topologies of DDR IPs with additional I/O features, such as DDR1/2 PHY, Mobile DDR PHY, Bonding-Over-Active-Circuit (BOAC) DDR PHY, are planned for future release.
 
About Faraday Technology Corporation

Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad silicon IP portfolio includes 32-bit RISC CPUs, DSPs, MPEG4, H.264, PHYs/Controllers for USB 2.0, Ethernet, Serial ATA, PCI Express, Cell Library and Memory Compiler. With more than 700 employees and 2006 revenue of US$171 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan , Faraday has service and support offices around the world, including the U.S. , Japan , Europe, and China . For more information, please visit:www.faraday-tech.com