Beach Solutions Ensures Higher Quality IP with Metric Driven Tool
SAN JOSE, Calif.-- June 28, 2007 --Beach Solutions, the leading provider of commercial tools to manage addressable registers and auto-generate SoC design integration deliverables, provides a powerful Design Rule Checker (DRC) engine in the new release of the Beach EASI Tools Suite version 3.8.
Architected to handle modern designs containing dozens of cores, the re-engineered DRC engine delivers results five times faster than previous versions to enable the engineer to more quickly check the quality of their designs at any level within the hierarchy, identify and fix specific failures, and release the design to synthesis.
Sophisticated Semantic Rule Checks
With an easily extensible set of more than 300 Design Rule Checks, EASI DRC 3.8 checks register and interface specification data for syntax errors, naming inconsistencies, duplicate items or missing reset values. The DRC also includes sophisticated semantic design rule checks that validate objects within context to ensure data integrity. For example, to avoid overlapping registers or illegal accesses, avoid overlapping IP blocks, identify conflicting set/clear registers, flag when a register data width conflicts with address bus width, to name just a few.
Graphical Quality Metrics
New graphical and textual IP quality metrics quickly highlight the presence of errors so that designers can immediately identify failures and then follow a hyperlink directly to the source of the error to immediately start working on a fix. EASI DRC pie charts, bar charts and summary tables reflect the success/failure of a data check and can be saved independently as part of a design sign-off or a QA assessment.
Security Watermark
Combining the new EASI DRC with the existing watermarking technology, allows the data check process to be controlled and only validate what has changed. This further improves productivity, and acts as a quality stamp that can be interrogated before the auto-generation process ensuring that design files used by development teams are created from proven sound data.
EASI DRC 3.8 is available with both EASI Core™ and EASI SoC™. EASI Core provides graphical data management tools and import utilities to package and deliver an IP block for accelerated integration and subsequent reuse in SoC designs. EASI SoC provides a graphical environment for managing the multi-level hierarchical systems in an SoC and auto-generates Register Transfer Level (RTL) code to describe the memory mapped registers and bus interface for each of the IP cores in a design.
About Beach Solutions
Beach Solutions is the leading provider of commercial tools to manage addressable registers and auto-generate SoC design integration deliverables. EASI Tools require no new language support, are simple to use, and fit neatly into existing design flows. Data is centralized in an XML database from which all hardware, software, verification and documentation deliverables are generated. All project team members then work from a common reference to deliver consistent design files throughout all phases of the development.
Further information is available from the Beach Solutions website: http://www.beachsolutions.com
|
Related News
- LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications
- Spectral Releases Advanced Quality Assurance & Data Analytics tool to validate advanced node Memory Compilers
- Synopsys Delivers Higher Productivity and Quality for Advanced-Node 5G/6G SoCs on Samsung Foundry's Low-Power Process
- Arm unveils new image signal processors to meet higher image quality requirements
- Videantis partners with Almalence for higher quality imaging
Breaking News
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- Veriest Solutions Strengthens North American Presence at DVCon US 2025
- Intel in advanced talks to sell Altera to Silverlake
- Logic Fruit Technologies to Showcase Innovations at Embedded World Europe 2025
- S2C Teams Up with Arm, Xylon, and ZC Technology to Drive Software-Defined Vehicle Evolution
Most Popular
- Intel in advanced talks to sell Altera to Silverlake
- Arteris Revolutionizes Semiconductor Design with FlexGen - Smart Network-on-Chip IP Delivering Unprecedented Productivity Improvements and Quality of Results
- RaiderChip NPU for LLM at the Edge supports DeepSeek-R1 reasoning models
- YorChip announces Low latency 100G ULTRA Ethernet ready MAC/PCS IP for Edge AI
- AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |