SmartSand announces SmartMerlins - Synthesis software

Sunnyvale, May 10, 2000 - Introducing the SmartMerlins™ tools for synthesis. Used for years with our service customers, SmartMerlins™ - Synthesis is now being offered as a tool suite product. Its main focus is to fully automate the synthesis flow, freeing designers to architect, develop and test the design.

SmartMerlins™ - Synthesis is the first commercially available tool designed to support both leading synthesis tools - Synopsys Design Compiler and Cadence Ambit Build Gates. By simply changing one variable in the smartsand.setup file, users can select either synthesis tool.

Setting up the tool is straightforward, just point the tool to the directories where your source code is stored, setup the desired programmable features in the .smartsand.setup file, specify the top-level constraints - and GO. Never write another synthesis script again!

Get a head start on isolating your timing problems by starting synthesis earlier in your project. The SmartMerlins™ automatically adapt a you add, delete, and change design modules. Only changed modules are resynthesized.

Resolving timing problems is typically a nightmarish task. Manually generate one file that indicates the modules that need to be resynthesized, and the type of operation effort spent or each module, or allow the report analyzer to analyze your timing reports to automatically determine and take the next step.

Utilize Multiple CPU Parallelism with Flowtracer

Through our strategic relationship with Runtime Design Automation (RTDA), our customers can take full advantage of a fully-automated parallel flow by using the SmartMerlins™ along with RTDA's Flowtracer product. The SmartMerlins™-Flowtracer combination allows you to reap maximum utilization of your synthesis licenses and CPU availability by executing independent synthesis tasks in parallel.

Toolset Features

Truly tool-neutral, currently supporting both Synopsys Design Compiler and Cadence Build Gates.
No Script writing needed, other than generation of the top-level constraints file.
Dependencies and execution order is determined by analyzing your source code- either in VHDL or verilog.
Source dates are tracked by the SmartMerlins™ and only changed modules are resynthesized.
Using the timing report analysis capability, automate the resynthesis of modules that fail to meet timing goals, with various optimiztion schemes.
Embed synthesis directives in your source code in tcl format-supported by both synthesis tools.
Allows for a design to be broken into submodules, each synthesized locally.
Supports Multiple CPU Platforms with Flowtracer.